Semiconductor package having a plurality of semiconductor chips stacked on a semiconductor substrate

A semiconductor package, comprising:

• a package substrate;
• a substrate adhesive member disposed on the package substrate;
• a plurality of semiconductor chips stacked on the substrate adhesive member in a vertical direction perpendicular to an upper surface of the package substrate and disposed to be offset in a horizontal direction perpendicular to the vertical direction, the plurality of semiconductor chips being sequentially stacked;
• and
• a conductive connection member connecting the package substrate and the plurality of semiconductor chips,
• wherein each of the plurality of semiconductor chips includes a semiconductor chip body, a chip pad disposed in the semiconductor chip body, an upper oxide layer covering an upper surface of the semiconductor chip body and exposing a portion of an upper surface of the chip pad, and a lower oxide layer covering a lower surface of the semiconductor chip body,
• wherein at least a portion of the upper oxide layer of semiconductor chips except for an uppermost semiconductor chip among the plurality of semiconductor chips has an oxide bonding region, and
• wherein a thickness of the upper oxide layer is smaller than a thickness of the substrate adhesive member.

A semiconductor package, comprising:

• a package substrate;
• a plurality of semiconductor chips stacked on the package substrate in a vertical direction perpendicular to an upper surface of the package substrate and disposed to be offset in a horizontal direction perpendicular to the vertical direction, the plurality of semiconductor chips including first and second semiconductor chips being sequentially stacked;
• and
• a conductive connection member connecting the package substrate and the plurality of semiconductor chips,
• wherein each of the plurality of semiconductor chips includes a semiconductor chip body, a chip pad disposed in the semiconductor chip body, an upper oxide layer covering an upper surface of the semiconductor chip body and exposing a portion of an upper surface of the chip pad, and a lower oxide layer covering a lower surface of the semiconductor chip body,
• wherein the upper oxide layer comprises a first material,
• wherein the lower oxide layer comprises a second material,
• wherein the upper oxide layer of the first semiconductor chip has an oxide bonding region between the first material and the second material in at least a portion of a first region in contact with the lower oxide layer of the second semiconductor chip,
• wherein the upper oxide layer does not have an oxide bonding region in a second region other than the first region, and
• wherein porosity of the first material of the oxide bonding region is lower than porosity of the first material of the second region.