Semiconductor package including support member

A semiconductor package comprising:

• a first substrate including a first insulating layer, and a first conductive pattern disposed in the first insulating layer;
• a first semiconductor chip disposed on the first substrate;
• a plurality of bumps, each bump including a first end having a first area and a second end having a second area,
• wherein the second end contacts an upper surface of the first semiconductor chip and is disposed between the first end and the first semiconductor chip,
• wherein a first width of the first area is greater than a second width of the second area, and
• wherein the first and second widths are measured in a direction parallel to an upper surface of the first substrate;
• an interposer disposed on the plurality of bumps, wherein the interposer includes a second insulating layer, and a second conductive pattern disposed in the second insulating layer;
• and
• a first connection member disposed between the interposer and the first substrate, wherein the first connection member is spaced apart from the first semiconductor chip,
• wherein the first connection member electrically connects the first conductive pattern to the second conductive pattern.

A semiconductor package comprising:

• a first substrate including a first insulating layer, and a first conductive pattern disposed in the first insulating layer;
• a first semiconductor chip mounted on the first substrate;
• an interposer disposed on the first substrate, and spaced apart from the first semiconductor chip, wherein the interposer includes a second insulating layer, and a second conductive pattern disposed in the second insulating layer;
• a support member disposed on a bottom surface of the second insulating layer and contacting an upper surface of the first semiconductor chip, wherein the support member includes a first lower pad and a bump disposed under the first lower pad;
• a first connection member disposed between the first substrate and the interposer, and spaced apart from the first semiconductor chip, wherein the first connection member connects the first conductive pattern to the second conductive pattern;
• a second substrate disposed on the interposer;
• and
• a second semiconductor chip mounted on the second substrate,
• wherein the bump includes a first end having a first area, and a second end having a second area disposed under the first end,
• wherein the first end of the bump contacts the first lower pad,
• wherein a first width of the first area is greater than a second width of the second area, and
• wherein the first and second widths of the bump are measured in a direction parallel to an upper surface of the first substrate.