Semiconductor component with metal-insulator-metal capacitor assembly

A semiconductor component comprising a multilayer interconnect structure, the multilayer interconnect structure comprising:

• electrical conductor lines and via connections embedded in layers of dielectric material;
• a conductive bottom plate on one or more conductor lines of a first level of the multilayer interconnect structure;
• a dielectric layer included in a second level of the multilayer interconnect structure, wherein the second level lies directly above the first level, wherein the dielectric layer is lying directly on the conductive bottom plate, and wherein the dielectric layer comprises a cavity through a full thickness of the dielectric layer and lying within boundaries of the conductive bottom plate;
• a plurality of pillars of dielectric material distributed on the conductive bottom plate;
• a stack of layers comprising electrically conductive layers including a bottom layer, a top layer, and at least one intermediate layer, wherein the stack of layers further comprises dielectric layers which separate the electrically conductive layers from each other, and wherein the stack of layers is arranged based on a topography defined by the conductive bottom plate, sidewalls of one or more pillars of the plurality of pillars, and sidewalls of the cavity;
• and
• a continuous layer of electrically conductive material that fills a remaining volume of the cavity and is in direct contact with the top layer of the stack of layers, wherein the pillars or several subgroups of pillars have different heights, and wherein each intermediate layer of the stack of layers and underlying layers of the intermediate layer are defined by a topography defined by top surfaces of one or more pillars, and wherein in separate areas above the top surfaces of one or more pillars, an upper surface of each intermediate layer is coplanar with an upper surface of the continuous layer;
• and
• a plurality of via connections of the second level of the multilayer interconnect structure, the plurality of via connections including:
• one or more via connections in direct contact with the upper surface of the continuous layer;
• one or more via connections in direct contact with each intermediate layer of the stack of layers in the one or more separate areas;
• and
• one or more via connections in direct or indirect contact with the bottom layer of the stack of layers, such that the stack of layers forms an assembly of capacitors comprising a plurality of capacitors, each capacitor formed by two adjacent ones of the electrically conductive layers of the stack of layers serving as two electrodes and one of the dielectric layers separating the two electrodes, and wherein a bottom electrode and a top electrode of the assembly of capacitors and each intermediate layer are contacted through the plurality of via connections of the second level.