Test vehicle and test method for microelectronic devices

A device comprising:

• a substrate;
• a test structure;
• a buried gate transistor;
• wherein said buried gate transistor comprises:
• a gate having a buried part buried in the substrate,
• a gate dielectric electrically insulating the gate from the substrate,
• a first contact of the buried gate transistor located on a first side of the gate, and
• a second contact of the buried gate transistor located on a second side of the gate, opposite the first side, and
• wherein said test structure comprises:
• a first test contact located on a side of the first contact of the buried gate transistor opposite the gate,
• a second test contact located on a side of the second contact of the buried gate transistor opposite the gate,
• a buried layer buried within the substrate and having a doping greater than or equal to 1018 cm−3 and having an upper face,
• a first insulation structure configured to electrically insulate the first test contact from the first contact of the buried gate transistor, and
• a second insulation structure configured to electrically insulate the second test contact from the second contact of the buried gate transistor, and
• wherein the first contact of the buried gate transistor and the second contact of the buried gate transistor each have a bottom face spaced above the upper face of the buried layer,
• wherein the first test contact and the second test contact each extend through a portion of the substrate and have a bottom face located within the buried layer,
• wherein the upper face of the buried layer is parallel to a bottom face of the gate dielectric, and
• wherein a plane of the upper face of the buried layer passes within the gate dielectric such that the buried layer intercepts a conduction path of the buried gate transistor.