Quantum bit chip having a stack of qubit wafers and spacer wafers, and a method for fabricating the quantum bit chip

A method for fabricating a qubit chip, the method comprising:

• fabricating two or more qubit wafers, wherein each of the two or more qubit wafers comprises a plurality of qubit devices;
• fabricating one or more spacer elements;
• alternately arranging the one or more spacer elements and the two or more qubit wafers on a common axis;
• and
• fabricating a conductive arrangement, wherein the conductive arrangement is configured to electrically connect the two or more qubit wafers,
• wherein the conductive arrangement comprises at least one superconducting via per each qubit wafer of the two or more qubit wafers and each spacer element of the one or more spacer elements, the at least one superconducting via passing through the two or more qubit wafers or the one or more spacer elements, and
• wherein the one or more spacer elements comprise one or more spacer wafers, and wherein a thickness of each spacer wafer of the one or more spacer wafers is larger than a thickness of each qubit wafer of the two or more qubit wafers.