Memory device including bottom electrode bridges and method of manufacture

A method comprising:

• forming a first bottom electrode bridge and a second bottom electrode bridge in a first dielectric layer;
• depositing a spin-orbit torque (SOT) layer structure on the first dielectric layer, the first bottom electrode bridge, and the second bottom electrode bridge;
• depositing a magnetic tunnel junction (MTJ) stack on the SOT layer structure;
• forming a patterned photoresist on the MTJ stack, wherein the patterned photoresist has a first width in a first direction greater than a first distance between the first bottom electrode bridge and the second bottom electrode bridge in the first direction, and less than a second distance between outer sidewalls of the first bottom electrode bridge and the second bottom electrode bridge;
• performing a first etching process on the MTJ stack and an upper portion of the SOT layer structure, wherein the first etching process forms a first upper sidewall and a second upper sidewall of the SOT layer structure;
• and
• after performing the first etching process performing a second etching process on a lower portion of the SOT layer structure, wherein the second etching process forms a first lower sidewall and a second lower sidewall of the SOT layer structure, wherein a first lateral distance between the first upper sidewall and the second upper sidewall is less than a second lateral distance between the first lower sidewall and the second lower sidewall, and wherein the second etching process ends on the first bottom electrode bridge and the second bottom electrode bridge.

A memory device comprising:

• a first dielectric layer on a semiconductor substrate, the first dielectric layer over a first via and a second via;
• a first bottom electrode in the first dielectric layer, the first bottom electrode on the first via, wherein first via side surfaces for the first via are disposed laterally within first electrode side surfaces for the first bottom electrode;
• a second bottom electrode in the first dielectric layer, the second bottom electrode on the second via, wherein second via side surfaces for the second via are disposed laterally within second electrode side surfaces for the second bottom electrode, wherein the first bottom electrode is spaced apart from the second bottom electrode along a first direction in a top-down view;
• a spin-orbit torque (SOT) structure on the first bottom electrode and the second bottom electrode, wherein outer SOT side surfaces for the SOT structure are laterally disposed within a perimeter defined by outer side surfaces for the first electrode side surfaces for the first bottom electrode and the second electrode side surfaces of the second bottom electrode, wherein along a second direction, the first bottom electrode extends laterally past edges of the SOT structure, wherein along the second direction, the second bottom electrode extends laterally past edges of the SOT structure, wherein the second direction is perpendicular to the first direction, wherein the first direction and the second direction are parallel to a major surface of the semiconductor substrate, wherein a bottom surface of the SOT structure is wider than a top surface of the SOT structure along the first direction, and wherein the top surface of the SOT structure overlaps the first bottom electrode and the second bottom electrode in a cross-sectional view;
• and
• a magnetic tunnel junction (MTJ) on the SOT structure, wherein a bottom surface of the MTJ overlaps the first bottom electrode and the second bottom electrode in a third direction perpendicular to the major surface of the semiconductor substrate, and wherein the bottom surface of the SOT structure is wider than the bottom surface of the MTJ along the first direction.