Fin field-effect transistor, ESD protection circuit, filter circuit, and electronic device
AssigneeHuawei Technologies Co., Ltd.
InventorQianming Zhu
Life of this patent
Estimating the term…
Abstract
A FinFET includes at least two fins arranged in parallel, a plurality of valid gates, and a first dummy polycrystalline silicon. The at least two fins extend in a first direction, and the plurality of valid gates and the first dummy polycrystalline silicon extend in a second direction and cover surfaces of the at least two fins. The first dummy polycrystalline silicon is located on one side of the plurality of valid gates, and fins on both sides of each of the plurality of valid gates are respectively a source terminal and a drain terminal of the FinFET. The plurality of valid gates is coupled to a gate terminal of the FinFET. The first dummy polycrystalline silicon is coupled between the gate terminal of the FinFET and a resistor potential terminal.
Claims20
A fin field-effect transistor (FinFET), comprising:
- a gate terminal;
- a source terminal;
- a drain terminal;
- a resistor potential terminal;
- valid gates coupled to the gate terminal;
- fins arranged in parallel to each other, extending in a first direction, and comprising:
- first fins disposed on a first side of the valid gates and coupled to the source terminal;
- and
- second fins disposed on a second side of the valid gates and coupled to the drain terminal;
- and
- a first dummy polycrystalline silicon layer located on the first side of the valid gates,
- wherein the valid gates and the first dummy polycrystalline silicon layer extend in a second direction and cover surfaces of the fins,
- wherein the first dummy polycrystalline silicon layer is coupled to and disposed between the gate terminal and the resistor potential terminal;
- a second dummy polycrystalline silicon layer located on the first second side of the valid gates, a first dummy gate located between the first dummy polycrystalline silicon layer and the valid gates;
- and
- a second dummy gate located between the second dummy polycrystalline silicon layer and the valid gates, wherein the first dummy gate and the second dummy gate are suspended.
Dependencies are inferred from the claim text.