Semiconductor device

A semiconductor device, comprising:

• a first logic cell and a second logic cell on a substrate, the first logic cell and the second logic cell being spaced apart from each other in a first direction;
• an isolation region between the first logic cell and the second logic cell;
• a first active pattern on the first logic cell and a second active pattern on the second logic cell;
• a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern;
• a trench on the isolation region;
• a first dummy gate electrode adjacent to a first sidewall of the trench and extending in a second direction intersecting the first direction;
• a gate electrode extending in the second direction on the first logic cell, and being spaced apart in the first direction from the first dummy gate electrode;
• and
• a separation pattern between the gate electrode and the first dummy gate electrode, the separation pattern extending in the second direction,
• wherein in the first logic cell, the separation pattern is between adjacent first source/drain patterns in the first direction,
• wherein a first gate spacer is on an upper sidewall of the separation pattern.

A semiconductor device, comprising:

• a substrate comprising a first logic cell, a second logic cell, and an isolation region between the first logic cell and the second logic cell, the first logic cell and the second logic cell being adjacent to each other in a first direction;
• a trench on the isolation region, the trench having a first sidewall adjacent to the first logic cell and a second sidewall adjacent to the second logic cell;
• a device isolation layer in a lower portion of the trench;
• a first active pattern and a second active pattern in the first logic cell and the second logic cell, respectively;
• a plurality of first source/drain patterns and a plurality of second source/drain patterns on the first active pattern and the second active pattern, respectively;
• a first channel pattern and a second channel pattern connected to the plurality of first source/drain patterns and the plurality of second source/drain patterns, respectively, each of the first and second channel patterns comprising a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and spaced apart from each other;
• a first dummy gate electrode on the first sidewall of the trench, the first dummy gate electrode extending in a second direction intersecting the first direction;
• a second dummy gate electrode on the second sidewall of the trench, the second dummy gate electrode extending in the second direction;
• a first gate electrode and a second gate electrode extending in the second direction across the first channel pattern and the second channel pattern, respectively, each of the first and second gate electrodes comprising a first part between the substrate and the first semiconductor pattern, a second part between the first semiconductor pattern and the second semiconductor pattern, a third part between the second semiconductor pattern and the third semiconductor pattern, and a fourth part on the third semiconductor pattern;
• a gate dielectric layer between the first channel pattern and the first gate electrode and between the second channel pattern and the second gate electrode;
• a dummy gate dielectric layer between the first channel pattern and the first dummy gate electrode and between the second channel pattern and the second dummy gate electrode;
• a first gate spacer on each of sidewalls of the first and second gate electrodes;
• a dummy gate spacer on each of sidewalls of the first and second dummy gate electrodes;
• a gate capping pattern on each of top surfaces of the first and second gate electrodes;
• a first separation pattern extending in the second direction between the first gate electrode and the first dummy gate electrode, wherein, in the first direction, the first separation pattern is between adjacent ones of the plurality of first source/drain patterns;
• a first interlayer dielectric layer on the gate capping pattern;
• an active contact penetrating the first interlayer dielectric layer, and being coupled to one of the pluralities of first and second source/drain patterns;
• and
• a gate contact penetrating the first interlayer dielectric layer, and being coupled to one of the first and second gate electrodes,
• wherein a top surface of the first separation pattern is at a same level as a top surface of the gate capping pattern.