Current sensing in power semiconductor devices

An III-nitride power semiconductor based heterojunction device comprising:

• a first heterojunction transistor comprising a first drain terminal, a first source terminal and a first gate terminal;
• a second heterojunction transistor comprising a second drain terminal, a second source terminal and a second gate terminal, wherein the second drain terminal is operatively connected to the first drain terminal, the second gate terminal is operatively connected to the first gate terminal;
• a resistive load comprising a first terminal operatively connected to the first source terminal and a second terminal operatively connected to the second source terminal;
• a monolithically integrated level shifting stage configured to receive an input signal corresponding to a signal across the resistive load and output a level shifted signal that corresponds to the input signal;
• an amplifier stage configured to receive the level shifted signal as an input and provide an output signal to an output node of the heterojunction device, wherein the output signal of the amplifier stage is proportional to the signal across the resistive load;
• and
• wherein the second heterojunction transistor has a substantially identical structure to the first heterojunction transistor, and wherein the second heterojunction transistor is scaled to a smaller area or gate perimeter than the first heterojunction transistor by a scale factor X, where X is larger than 1;
• wherein the level shifting stage comprises a bridge circuit, the bridge circuit comprising a first leg and a second leg;
• wherein the first leg comprises a first level shifter configured to receive the input signal corresponding to the signal across the resistive load and output the level shifted signal;
• wherein the second leg comprises a second level shifter configured to output a reference signal;
• and
• wherein the second level shifter comprises at least one component which is matched or ratiometrically matched in geometry and performance to a component within the first level shifter;
• wherein the amplifier stage comprises a differential amplifier structure;
• and
• wherein the differential amplifier structure is configured to receive the level shifted signal as a first input and the reference signal as a second input.