Semiconductor transistor structure and fabrication method thereof

A method of forming a semiconductor transistor structure, comprising:

• providing a semiconductor substrate having an active area and a trench isolation region surrounding the active area;
• forming a first inter-layer dielectric (ILD) layer covering the semiconductor substrate;
• forming a metal gate embedded in the first ILD layer and overlying the active area and the trench isolation region, wherein the metal gate comprises a first portion disposed directly above the active area and a second portion disposed directly above the trench isolation region, wherein the first portion is thicker than the second portion;
• forming a source doping region on a first side of the metal gate;
• forming a drain doping region on an opposing second side of the metal gate;
• forming a hard mask layer on the second portion of the metal gate;
• and
• forming a gate dielectric layer between the first portion of the metal gate and the active area;
• forming a second inter-layer dielectric (ILD) layer covering the first ILD layer, the hard mask layer, and the metal gate;
• and
• forming a contact plug embedded in the second ILD layer and extending into the hard mask layer to electrically contact with the second portion of the metal gate.