US 12,745,429 B2Granted

Diffusion cut stressors for stacked transistors

AssigneeIntel Corporation

InventorsCheng-Ying Huang, Munzarin F. Qayyum, Nicole K. Thomas, Rohit Galatage, Patrick Morrow, Jami A. Wiedemer, Marko Radosavljevic, Jack T. Kavalieros

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

Techniques are provided herein to form non-planar semiconductor devices in a stacked transistor configuration adjacent to stressor materials. In one example, an n-channel device and a p-channel device may both be gate-all-around transistors each having any number of nanoribbons extending in the same direction, where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and both ends of the p-channel device. On the opposite side of the stacked source or drain regions (e.g., opposite from the nanoribbons), stressor materials may be used to fill the gate trench in place of additional semiconductor devices. The stressor materials may include, for instance, a compressive stressor material adjacent to the p-channel device and/or a tensile stressor material adjacent to the n-channel device. The stressor material(s) may form or otherwise be part of a diffusion cut structure.

Claims20

Dependent claims

An integrated circuit, comprising:

a first semiconductor device having one or more first bodies of semiconductor material extending in a first direction from a first source or drain region to a second source or drain region;
a second semiconductor device having one or more second bodies of semiconductor material extending in the first direction from a third source or drain region to a fourth source or drain region, wherein the one or more second bodies of semiconductor material are spaced vertically from the one or more first bodies of semiconductor material in a second direction different from the first direction, the third source or drain region is spaced vertically from the first source or drain region in the second direction;
a first spacer structure extending between and contacting ends of the one or more first bodies of semiconductor material and ends of the one or more second bodies of semiconductor material, the first spacer structure extending in the second direction from a first horizontal plane at its bottommost surface to a second horizontal plane at its topmost surface;
a second spacer structure extending in the second direction from the first horizontal plane to the second horizontal plane, the first source or drain region and the third source or drain region between the first spacer structure and the second spacer structure;
and
a stressor material adjacent to the second spacer structure, such that at least a portion of the second spacer structure is between the stressor material and the first source or drain region.

3 more elements

An electronic device, comprising:

a chip package comprising one or more dies, at least one of the one or more dies comprising
a first semiconductor device having one or more first semiconductor nanoribbons extending in a first direction between a first source or drain region and a second source or drain region;
a second semiconductor device having one or more second semiconductor nanoribbons extending in the first direction between a third source or drain region and a fourth source or drain region, wherein the one or more second semiconductor nanoribbons are spaced vertically from the one or more first semiconductor nanoribbons in a second direction different from the first direction, the third source or drain region is spaced vertically from the first source or drain region in the second direction;
a first spacer structure extending between and contacting ends of the one or more first semiconductor nanoribbons and ends of the one or more second semiconductor nanoribbons in the second direction;
a second spacer structure extending in the second direction, wherein the first source or drain region and the third source or drain region are between the first spacer structure and the second spacer structure, and wherein a height of the second spacer structure along the second direction is substantially equal to a height of the first spacer structure along the second direction;
and
a stressor material adjacent to the second spacer structure, wherein a portion of the second spacer structure is between the stressor material and the first source or drain region.

4 more elements

An integrated circuit, comprising:

a first semiconductor device having one or more first semiconductor nanoribbons extending in a first direction between a first p-doped source or drain region and a second p-doped source or drain region;
a second semiconductor device having one or more second semiconductor nanoribbons extending in the first direction between a first n-doped source or drain region and a second n-doped source or drain region, wherein the one or more second semiconductor nanoribbons are spaced vertically from the one or more first semiconductor nanoribbons in a second direction different from the first direction, the first n-doped source or drain region is spaced vertically from the first p-doped source or drain region in the second direction;
a first spacer structure extending between and contacting ends of the one or more first semiconductor nanoribbons and ends of the one or more second semiconductor nanoribbons in the second direction;
a second spacer structure extending in the second direction, such that the first n-doped source or drain region and the first p-doped source or drain region are between the first spacer structure and the second spacer structure, wherein an uppermost surface of the first spacer structure is coplanar with an uppermost surface of the second spacer structure, and a lowermost surface of the first spacer structure is coplanar with a lowermost surface of the second spacer structure;
a compressive stressor material adjacent to the second spacer structure, such that a portion of the second spacer structure is between the compressive stressor material and the first p-doped source or drain region;
and
a tensile stressor material adjacent to the second spacer structure, such that a portion of the second spacer structure is between the tensile stressor material and the first n-doped source or drain region.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/809,329Filed 28 Jun 2022
Published: US 2023/0420562 A128 Dec 2023
Granted: 22 Sep 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/6735
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: having gates fully surrounding the channels, e.g. gate-all-around
H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile