Semiconductor structure

A semiconductor structure, comprising:

• circuit cells, wherein each of the circuit cells comprises:
• nanostructures vertically stacked from each other;
• and
• gate structures wrapping around the nanostructures and extending in a first direction;
• dielectric gate structures extending in the first direction and separating the circuit cells from each other in a second direction that is perpendicular to the first direction;
• gate spacers on sidewalls of the gate structures and the dielectric gate structure;
• first source/drain features, wherein a first one of the first source/drain features is between adjacent two of the gate structures;
• second source/drain features, wherein a first one of the second source/drain features is between one of the gate structures and one of the dielectric gate structures;
• a first silicide feature over the first one of the first source/drain features and a second silicide feature over the first one of the second source/drain features;
• a first source/drain contact over the first one of the first source/drain features and extending in the first direction;
• a second source/drain contact over the first one of the second source/drain features and extending in the first direction, wherein a width of the second source/drain contacts is greater than a width of the first source/drain contact;
• and
• a contact sidewall layer on a sidewall of the second source/drain contact, wherein a bottom point of an outer sidewall of the contact sidewall layer intersects with a top point of an outer sidewall of the second silicide feature, and a bottom point of the outer sidewall of the second silicide feature intersects with a top point of an outer sidewall of the first one of the second source/drain features.

A semiconductor structure, comprising:

• a circuit cell, wherein the circuit cell comprises:
• a first gate structure extending in a first direction and wrapping around first nanostructures vertically stacked from each other;
• and
• a second gate structure extending in the first direction, wrapping around second nanostructures that are vertically stacked from each other, and adjacent to the first gate structure in a second direction that is perpendicular to the first direction;
• a dielectric gate structure extending in the first direction and on a cell boundary of the circuit cell;
• a first source/drain feature between the first gate structure and the second gate structure;
• a second source/drain feature between the second gate structure and the dielectric gate structure;
• a first source/drain contact over the first source/drain feature and having a first width in the second direction;
• and
• a second source/drain contact over the second source/drain feature and having a second width greater than the first width in the second direction, wherein the second source/drain contact extends in the first direction across the cell boundary of the circuit cell in a top view, wherein a distance from the second source/drain contact to the second gate structure at a first level is greater than a distance from the second source/drain contact to the dielectric gate structure at the first level.