Gate-all-around integrated circuit structures having fin stack isolation

A method of fabricating an integrated circuit structure, the method comprising:

• forming a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls;
• forming an isolation structure on the top and along the sidewalls of the sub-fin structure;
• forming a vertical arrangement of horizontal nanowires on the isolation structure and vertically over the top surface of the sub-fin structure;
• and
• forming a gate endcap structure parallel with and laterally spaced apart from the vertical arrangement of horizontal nanowires, wherein a portion of the gate endcap structure is continuous with a portion of the isolation structure vertically between the sub-fin structure and the vertical arrangement of horizontal nanowires, and wherein the gate endcap structure comprises a single dielectric material layer extending from below the top of the sub-fin to above a bottom nanowire of the vertical arrangement of horizontal nanowires.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls;
• an isolation structure on the top and along the sidewalls of the sub-fin structure;
• a vertical arrangement of horizontal nanowires on the isolation structure and vertically over the top surface of the sub-fin structure;
• and
• a gate endcap structure parallel with and laterally spaced apart from the vertical arrangement of horizontal nanowires, wherein a portion of the gate endcap structure is continuous with a portion of the isolation structure vertically between the sub-fin structure and the vertical arrangement of horizontal nanowires, and wherein the gate endcap structure comprises a single dielectric material layer extending from below the top of the sub-fin to above a bottom nanowire of the vertical arrangement of horizontal nanowires.