Memory device including tiers of FeFET memory cells and vertical control gates

An apparatus comprising:

• tiers located one over another, each of the tiers including memory cells, the tiers including a first tier and a second tier;
• a first conductive structure extending through the tiers;
• a first memory cell included in the memory cells of the first tier, the first memory cell including:
• a first ferroelectric portion adjacent a first portion of the first conductive structure;
• a first charge storage structure adjacent the first ferroelectric portion;
• a first dielectric portion adjacent the first charge storage structure;
• and
• a first semiconductor portion adjacent the first dielectric portion;
• a second memory cell included in the memory cells of a second tier of the tiers, the second memory cell including:
• a second ferroelectric portion adjacent a second portion of the first conductive structure;
• a second charge storage structure adjacent the second ferroelectric portion;
• a second dielectric portion adjacent the second charge storage structure;
• and
• a second semiconductor portion adjacent the second dielectric portion;
• a first additional conductive structure located in the first tier and adjacent a first side of the first semiconductor portion;
• a second additional conductive structure located in the first tier and adjacent a second side of the first semiconductor portion;
• a third additional conductive structure located in the second tier and adjacent a first side of the second semiconductor portion;
• and
• a fourth additional conductive structure located in the second tier and adjacent a second side of the second semiconductor portion, wherein each of the first, second, third, and fourth additional conductive structures has a length perpendicular to a direction from the first tier to the second tier.

A method comprising:

• forming levels of first dielectric materials interleaved with levels of second dielectric materials;
• forming an opening through the levels of first dielectric materials and the levels of second dielectric materials to expose, at the opening, a portion of a level of dielectric material among the levels of first dielectric materials and the levels of second dielectric materials;
• removing at least part of the portion of the level of dielectric material to form a recess in the level of dielectric material;
• and
• forming a memory cell in the recess, including:
• forming a semiconductor material in the recess;
• forming a dielectric material adjacent the semiconductor material;
• forming a charge storage material adjacent the dielectric material;
• forming a ferroelectric material adjacent the charge storage material;
• forming a conductive material in adjacent the dielectric material;
• and
• forming an additional conductive material adjacent the semiconductor material.

A method comprising:

• forming levels of first dielectric materials interleaved with levels of second dielectric materials;
• forming a first opening and a second opening through the levels of first dielectric materials and the levels of second dielectric materials to expose a first portion of a level of dielectric material among the levels of first dielectric materials and the levels of second dielectric materials, and to expose a second portion of the level of dielectric material at the second opening;
• removing at least part of the first portion to form a first recess in the level of dielectric material, and removing at least part of the second portion to form a second recess in the level of dielectric material;
• forming, in each of the first and second recesses, a semiconductor material, a dielectric material adjacent the semiconductor material, a charge storage material adjacent the dielectric material, a ferroelectric material adjacent the charge storage material, and a conductive material adjacent the dielectric material;
• removing a portion of the levels of first dielectric materials interleaved with the levels of second dielectric materials to expose a portion of the semiconductor material formed in the first recess and a portion of the semiconductor material formed in the second recess;
• forming a first conductive material adjacent the portion of the semiconductor material in the first recess;
• and
• forming a second conductive material adjacent the portion of the semiconductor material in the second recess.