Image sensing device including test pattern

An image sensing device comprising,

• a pixel array including pixel units configured to generate photocharge in response to incident light, the pixel units including a plurality of first pixel transistors located in different rows of the pixel array;
• a plurality of first upper signal lines respectively connected to the plurality of first pixel transistors;
• a first test line, separated from and commonly connected to, the plurality of first upper signal lines;
• a first test pad connected to the first test line and configured to provide a first test signal to the first test line;
• and
• a first test transistor connected to the first test line and the first test pad and configured to enable or disable a test operation by selectively providing the first test signal to the first test line,
• wherein during the test operation, the first test signal is provided to the plurality of first pixel transistors located in different rows of the pixel array through the first test transistor, the first test line, and the plurality of first upper signal lines,
• wherein the pixel array further includes:
• a plurality of second upper signal lines respectively connected to a plurality of second pixel transistors;
• a second test line separate from and commonly connected to, the plurality of second upper signal lines;
• a second test pad connected to the second test line and configured to provide a second test signal to the second test line;
• and
• a second test transistor connected to the second test line and the second test pad.

An image sensing device, comprising:

• a pixel array located in a first substrate layer and configured to receive incident light and generate photocharge in response to the incident light;
• a plurality of first pixel transistors located in an arbitrary row included in the pixel array;
• a first upper signal line connected to the plurality of first pixel transistors and located in the first substrate layer;
• a first test line connected to the first upper signal line and located in the first substrate layer;
• a first lower signal line connected to the first upper signal line and located in a second substrate layer below the first substrate layer;
• and
• a first test transistor connected to the first lower signal line and a first test pad,
• wherein the first test line, the first test transistor and the first test pad are provided to test the plurality of first pixel transistors, and
• wherein
• during a sensing operation, a first control signal for the first pixel transistor is provided to the plurality of first pixel transistors through the first lower signal line and the first upper signal line, and
• during a test operation, a first test signal provided through the first test pad is provided to the plurality of first pixel transistors without passing through the first lower signal line.