Layout for imaging system and pixel cell array with quad row select transistors

A pixel cell array disposed in or on a semiconductor material, comprising:

• a plurality of pixel cells arranged into rows and columns including a first pixel cell and a second pixel cell adjacent to the first pixel cell, wherein each pixel cell included in the plurality of pixel cells includes:
• one or more photodiodes configured to generate image charge in response to incident light;
• a floating diffusion coupled to receive the image charge generated by the one or more photodiodes;
• a source-follower transistor having a gate coupled to the floating diffusion to generate an image signal at a first source/drain region of the source-follower transistor in response to the image charge in the floating diffusion;
• a first row select transistor having a first source/drain region coupled to the first source/drain region of the source-follower transistor to output the image signal;
• and
• a second row select transistor having a first source/drain region coupled to a second source/drain region of the first row select transistor, and
• a common junction disposed in the semiconductor material, wherein the first source/drain regions of the second row select transistors included in the first and the second pixel cells are coupled together through the common junction.