Equalizer with all-pass filter delay
AssigneeCisco Technology, Inc.
InventorsKadaba Lakshmikumar, Abhishek Bhat, Romesh Kumar Nandwana
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Abstract
The present disclosure describes an equalizer that uses an all-pass filter to delay a signal to a transconductor cell. According to an embodiment, the equalizer includes an input line, a first transconductor cell connected to the input line, a filter, and a second transconductor cell. The filter includes a first inverter connected to the input line, a second inverter connected to an output of the first inverter, and a third inverter connected to the input line and the output of the second inverter. The second transconductor cell is connected to the output of the second inverter.
Claims20
An equalizer comprising:
- an input line;
- a first transconductor cell connected to the input line;
- a filter comprising:
- a first inverter connected to the input line;
- a second inverter connected to an output of the first inverter;
- and
- a third inverter connected to the input line and the output of the second inverter;
- and
- a second transconductor cell connected to the output of the second inverter.
A method comprising:
- providing a transconductance using a first transconductor cell connected to an input line;
- delaying, using a filter, a signal, wherein the filter comprises (i) a first inverter connected to the input line, (ii) a second inverter connected to an output of the first inverter, and (iii) a third inverter connected to the input line and the output of the second inverter;
- and
- providing a transconductance using a second transconductor cell connected to the output of the second inverter.
An equalizer comprising:
- an input line;
- a first transconductor cell of a main cursor of the equalizer;
- an all-pass filter comprising:
- a first inverter connected to the input line;
- a second inverter connected to an output of the first inverter;
- and
- a third inverter connected to the input line and the output of the second inverter, wherein the all-pass filter is arranged to delay a signal from the input line;
- and
- a second transconductor cell of a post-cursor of the equalizer, wherein the second transconductor cell is connected to the output of the second inverter, and wherein the second transconductor cell is arranged to receive the signal from the all-pass filter.
Dependencies are inferred from the claim text.