Systems for providing synchronized FFE in SerDes transmitters
AssigneeSamsung Electronics Co., Ltd.
InventorsUmamaheswara Reddy Katta, Tamal Das
Life of this patent
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Abstract
There is provided a system and a method for filtering out glitches in a SerDes transmitter. The SerDes transmitter includes a latency generation block, and a 2-to-1 serializer. The latency generation block is configured to synchronize a feed forward equalization (FFE) enable signal to a half rate domain by creating a latency in the FFE enable signal, and provide the synchronized FFE enable signal to a plurality of synchronized FFE selection multiplexers. The SerDes transmitter further includes a 2-to-1 serializer that is configured to filter out a glitch using the synchronized FFE enable signal in the half rate domain.
Claims10
A serializer/deserializer (SerDes) transmitter comprising:
- a latency generation circuit configured to:
- synchronize a feed forward equalization (FFE) enable signal to a half rate domain based on a latency in the FFE enable signal, the latency being equal to a latency in a first serializer configured to serialize input data;
- and
- provide the synchronized FFE enable signal in the half rate domain to a plurality of synchronized FFE selection multiplexers (MUXes);
- and
- a 2-to-1 serializer circuit configured to filter out a glitch using the synchronized FFE enable signal in the half rate domain in the plurality of synchronized FFE selection MUXes based on the synchronized FFE enable signal.
A method of filtering out a glitch in a serializer/deserializer (SerDes) transmitter, the method comprising:
- synchronizing a feed forward equalization (FFE) enable signal to a half rate domain based on a latency in the FFE enable signal, the latency being equal to a latency in a first serializer configured to serialize input data;
- providing the synchronized FFE enable signal in the half rate domain to a plurality of synchronized FFE selection multiplexers (MUXes);
- and
- filtering out a glitch in the plurality of synchronized FFE selection MUXes based on the synchronized FFE enable signal.
An apparatus comprising:
- a first serializer configured to serialize input data;
- a latency generation circuit configured to output a synchronized feed forward equalization (FFE) enable signal based on a latency in the FFE enable signal;
- a plurality of synchronized FFE selection multiplexers (MUXes) enabled based on the synchronized FFE enable signal;
- and
- a second serializer circuit configured to filter an output of the plurality of synchronized FFE selection MUXes by moving the FFE enable signal to a half rate data domain.
Dependencies are inferred from the claim text.