Data receiving circuit and memory

A data receiving circuit, comprising:

• a comparator for receiving initial input data and an initial reference voltage, wherein the comparator is configured to amplify a voltage difference between the initial input data and the initial reference voltage and output double-ended signals as a result of the amplification;
• and
• a plurality of data paths, comprising a first data path to an M-th data path, numbered in ascending order of natural numbers, with an i-th data path being any one of the plurality of data paths, and 1≤i≤M, M≥2;
• wherein each of the plurality of data paths receives the double-ended signals, the i-th data path is configured to sample based on an i-th clock to obtain an i-th bit data, and the i-th data path comprises:
• an adjustment circuit for receiving a previous second bit data to a previous N-th bit data prior to the i-th bit data, with 2≤N≤M, wherein the adjustment circuit is configured to adjust a voltage difference between the double-ended signals based on the previous second bit data to the previous N-th bit data to generate double-ended adjustment signals;
• and
• a sampling circuit for receiving the double-ended adjustment signals, the i-th clock, and a previous first bit data prior to the i-th bit data, wherein the sampling circuit is configured to, during a valid period of the i-th clock, compare and amplify a voltage difference between the double-ended adjustment signals based on the previous first bit data and output the i-th bit data.