Dual CML echo canceller with single-ended to differential conversion
AssigneeSamsung Electronics Co., Ltd.
InventorsAli Fazli Yeknami, Haritha Eachempatti
Life of this patent
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Abstract
A system may include a signal replica transmitter configured to generate a replica signal based on a first signal, and an echo canceller configured to remove crosstalk from a second signal. The echo canceller may include a first current mode logic (CML) circuit configured to receive a first set of input signals, and a second CML circuit configured to receive a second set of input signals, wherein a first output from the first CML circuit and a second output from the second CML circuit may be combined to remove the crosstalk from the second signal and generate an output signal from the echo canceller.
Claims16
A system comprising:
- a signal replica transmitter configured to generate a replica signal based on a first signal;
- and
- an echo canceller configured to remove crosstalk from a second signal, the echo canceller comprising:
- a first current mode logic (CML) circuit configured to receive a first set of input signals;
- and a second CML circuit configured to receive a second set of input signals, wherein a first output from the first CML circuit and a second output from the second CML circuit are combined to remove the crosstalk from the second signal and generate an output signal from the echo canceller;
- wherein the first signal is generated by a near-end transmitter (NETX) of a first electronic device, and the second signal comprises a third signal generated by a far-end transmitter (FETX) of a second electronic device and the crosstalk from the first electronic device;
- wherein the first set of input signals comprises the replica signal, the first CML circuit comprises a first transistor and a second transistor, the replica signal is applied to a gate of the first transistor, and the replica signal is applied to a gate of the second transistor.
A method, comprising:
- generating, by a replica transmitter, a replica signal based on a first signal;
- and removing, by an echo canceller, crosstalk from a second signal, the echo canceller comprising:
- a first current mode logic (CML) circuit configured to receive a first set of input signal signals;
- and a second CML circuit configured to receive a second set of inputs signals, wherein a first output from the first CML circuit and a second output from the second CML circuit are combined to remove the crosstalk from the second signal and generate an output signal from the echo canceller;
- wherein the first signal is generated by a near-end transmitter (NETX), and the second signal comprises a third signal generated by a far-end transmitter (FETX) and the crosstalk;
- wherein the first set of input signals comprises the replica signal, the first CML circuit comprises a first transistor and a second transistor, the replica signal is applied to a gate of the first transistor, and the replica signal is applied to a gate of the second transistor.
Dependencies are inferred from the claim text.