Super-lattice castellated field effect transistor (SLCFET) switch system

A method for fabricating a super-lattice castellated field effect transistor (SLCFET), the method comprising:

• forming a plurality of SLCFETs in a series stack between a first port and a second port to provide a propagation path of a radio frequency (RE) signal between the first port and the second port in response to activation of the SLCFETs;
• forming a plurality of gate resistors interconnecting gate terminals associated with each of the respective SLCFETs and an activation port;
• and
• forming a plurality of balancing resistors coupled to the gate terminals associated with each of the respective SLCFETs, the balancing resistors being configured to provide a current path for a balancing current associated with the RF signal, wherein the balancing current is approximately equal to a gate current through each of the gate resistors when the SLCFETs are activated.

A complement switch system comprising:

• an input/output (I/O) port impedance matching network arranged between an I/O port and a complement node;
• an I/O terminal impedance matching network arranged between an I/O terminal and the common node;
• a first super-lattice castellated field effect transistor (SLCFET) system comprising:
• a first plurality of SLCFETs arranged in a first series stack between the complement node and a low voltage rail to provide a propagation path of a radio frequency (RF) signal between the complement node and the low-voltage rail in response to activation of the first SLCFETs;
• a first plurality of gate resistors interconnecting gate terminals associated with each of the respective first SLCFETs and a first activation port to which an activation signal is provided to concurrently activate the first SLCFETs;
• and
• a first plurality of balancing resistors coupled to the gate terminals associated with each of the respective first SLCFETs, the first balancing resistors being configured to provide a first current path for a first balancing current associated with the RF signal to approximately equalize a drain-gate voltage and a gate-source voltage associated with each of the first SLCFETs when activated, wherein the first balancing current is approximately equal to a gate current through each of the gate resistors when the SLCFETs are activated;
• and
• a second SLCFET system comprising:
• a second plurality of SLCFETs arranged in a second series stack between the common node and the complement node to provide a propagation path of the RF signal between the common node and the complement node in response to activation of the second SLCFETs;
• a second plurality of gate resistors interconnecting the gate terminals associated with each of the respective second SLCFETs and a second activation port to which a complement of the activation signal is provided to concurrently activate the second SLCFETs;
• and
• a second plurality of balancing resistors coupled to the gate terminals associated with each of the respective second SLCFETs, the second balancing resistors being configured to provide a second current path for a second balancing current associated with the RF signal to approximately equalize a drain-gate voltage and a gate-source voltage associated with each of the second SLCFETs when activated, wherein the second balancing current is approximately equal to a gate current through each of the gate resistors when the SLCFETs are activated.