Self-calibrating digital to analog converter
AssigneeNXP USA, Inc.
InventorsRonak Prakashchandra Trivedi, Hanqing Xing, Jean CauXuan Le
Life of this patent
Estimating the term…
Loading patent…
AssigneeNXP USA, Inc.
InventorsRonak Prakashchandra Trivedi, Hanqing Xing, Jean CauXuan Le
Estimating the term…
The disclosure relates to self-calibration of non-linearity in a digital to analog converter (DAC). Example embodiments include a method for calibrating non-linearity of a segmented non-binary DAC in a self-calibrating DAC system, the method comprising: providing first calibration input digital signals to a thermometric weighted segment and measuring first outputs of the DAC with an ADC; providing second calibration input digital signals to the thermometric weighted segment and measuring second outputs of the DAC with the ADC; calculating a first scaling factor for first switches and resistive elements by dividing each of the second outputs of the DAC by a difference between adjacent ones of the first outputs of the DAC; calculating a second scaling factor for second switches from a sum of the first outputs of the DAC divided by a measured output range of the DAC; and storing the first and second scaling factors in a memory module.
A method for calibrating non-linearity of a segmented non-binary DAC in a self-calibrating DAC system, the segmented non-binary DAC having a thermometric weighted segment having a first plurality of switches and resistive elements controllable by a most significant plurality of bits of a digital input signal and a sub-binary weighted segment having a second plurality of switches and resistive elements controllable by a least significant plurality of bits of the digital input signal, the method comprising:
A self-calibrating DAC system comprising:
A computer program comprising instructions to cause a computer processor to perform a method of calibrating non-linearity of a segmented non-binary DAC in a self-calibrating DAC system, the segmented non-binary DAC having a thermometric weighted segment having a first plurality of switches and resistive elements controllable by a most significant plurality of bits of a digital input signal and a sub-binary weighted segment having a second plurality of switches and resistive elements controllable by a least significant plurality of bits of the digital input signal, the method comprising:
Dependencies are inferred from the claim text.