Electronic device and method for analog computing circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsChang-Woo Shin, Minje Kim, Sungmeen Myung
Life of this patent
Estimating the term…
Abstract
An electronic device includes an analog computing circuit comprising a plurality of rows comprising a plurality of first rows to which a data signal for computations is input and one or more second rows to which a calibration signal for error calibration is input, and a plurality of columns connected to the plurality of rows and configured to output a computation result in which an error is calibrated, by accumulating signals transmitted from the connected plurality of rows in response to an input of the data signal and the calibration signal.
Claims20
An electronic device comprising:
- an analog computing circuit comprising:
- a plurality of rows comprising a plurality of first rows to which a data signal for computations is input and one or more second rows to which a calibration signal for error calibration is input;
- and
- a plurality of columns connected to the plurality of rows and configured to output a computation result in which an error is calibrated, by accumulating signals transmitted from the connected plurality of rows in response to an input of the data signal and the calibration signal.
A processor-implemented method comprising:
- inputting a data signal for computations to a plurality of first rows of an analog computing circuit and inputting a calibration signal for error calibration to one or more second rows of the analog computing circuit;
- and
- outputting a computation result in which an error is calibrated, by accumulating signals transmitted from a plurality of rows through a plurality of columns connected to the plurality of rows in response to an input of the data signal and the calibration signal,
- wherein the plurality of rows comprises the plurality of first rows and the one or more second rows.
A manufacturing method comprising:
- computing a calibration value for each of a plurality of columns comprised in an analog computing circuit by analyzing an output of the analog computing circuit;
- determining a calibration value for one or more analog-to-digital converters (ADCs) connected to the plurality of columns based on the calibration value for each of the plurality of columns;
- determining a calibration signal to be input to the analog computing circuit for error calibration, one or more second rows to which the calibration signal is input, and a weight value of resistive elements connecting the one or more second rows to the plurality of columns for the error calibration, based on the calibration value for each of the plurality of columns and the calibration value for the one or more ADCs;
- and
- setting the analog computing circuit to have the calibration signal, the one or more second rows, and the weight value of the resistive elements.
Dependencies are inferred from the claim text.