Phase locked loop circuit and method of operation thereof

A method of operating a phase-locked loop circuit, the method comprising:

• adjusting a phase gain from a first value to a second value in response to a phase difference between a reference clock signal and a feedback clock signal being less than a reference value;
• generating a first control signal and a second control signal based on the adjusted phase gain;
• generating a lock detection signal based on the phase difference, the lock detection signal being activated in response to the phase gain having the second value and the lock detection signal being deactivated in response to the phase gain having the first value;
• generating a loop filter input signal by precharging an output node based on the first control signal and discharging the output node based on the second control signal;
• adjusting an impedance of a loop filter by switching a first switch connected in series with a resistor of the loop filter based on the lock detection signal;
• generating a loop filter output signal by filtering the loop filter input signal based on the adjusted impedance;
• and
• generating a clock signal based on the loop filter output signal.

A phase locked loop circuit comprising:

• a phase-frequency detection circuit configured to:
• receive a reference clock signal and a feedback clock signal,
• adjust a phase gain from a first value to a second value in response to a phase difference between the reference clock signal and the feedback clock signal being less than a reference value, and
• generate a first control signal and a second control signal based on the phase gain;
• a lock detection circuit configured to generate a lock detection signal that is activated in response to the phase gain having the second value;
• a charge pump circuit configured to generate a loop filter input signal by precharging an output node based on the first control signal and discharging the output node based on the second control signal;
• a loop filter comprising at least one resistor, at least one capacitor, and a first switch connected in series with the at least one resistor, the loop filter configured to:
• adjust a resistance value of the at least one resistor or a capacitance value of the at least one capacitor by switching the first switch based on the lock detection signal, and
• generate a loop filter output signal by filtering the loop filter input signal based on the adjusted resistance value or the adjusted capacitance value;
• and
• an oscillator configured to generate a clock signal based on the loop filter output signal.