Digital clock data recovery circuit and method for locking frequency of recovery clock signal thereof

Abstract

A digital clock data recovery circuit is provided and includes a phase lock loop circuit and a frequency lock loop circuit coupled to the phase lock loop circuit. The phase lock loop circuit generates a recovery clock signal according to a pre-divider value, a feedback divider value, and an input reference clock signal. The frequency lock loop circuit adjusts one of the pre-divider value and the feedback divider value according to the input reference clock signal and an input data clock signal, thereby locking a frequency of the recovery clock signal to a frequency of the input data clock signal. The frequency lock loop circuit is implemented by a digital circuit. The digital clock data recovery circuit operates in a data recovery mode after the frequency of the recovery clock signal is locked.

Dependencies are inferred from the claim text.