Shock recovery

A clock generation system, comprising:

• an oscillator circuit configured to electronically generate an oscillator clock;
• a mechanical oscillating sensor comprising a mechanical oscillator, and configured to generate a PLL input clock;
• a phase locked loop (PLL) configured to receive the PLL input clock, and to generate a PLL clock and a PLL feedback signal based on the PLL input clock;
• a clock multiplexer configured to conditionally connect the PLL clock and the oscillator clock to an output for a system clock;
• an acceleration sensor configured to sense an acceleration in each of one, two or three orthogonal spatial dimensions, and to generate acceleration measurements for each of the sensed spatial dimensions;
• and
• a shock recovery circuit, configured to receive one or more of the PLL input clock, the PLL feedback signal, and the acceleration measurements, and to generate a multiplexer control signal configured to cause the clock multiplexer to connect a particular one of the PLL clock and the oscillator clock to the output based on one or more of the PLL input clock, the PLL feedback signal, and the acceleration measurements, wherein the multiplexer control signal causes the clock multiplexer to connect the oscillator clock to the output in response to one or more of the received PLL input clock, the received PLL feedback signal, and the received acceleration measurements indicating a shock event.

A method of using a clock generation system, the method comprising:

• generating an oscillator clock;
• generating a PLL input clock;
• generating a PLL clock based on the PLL input clock;
• generating a system clock based on the PLL clock;
• monitoring the PLL clock;
• generating a PLL status signal based on the monitored PLL clock;
• monitoring an acceleration of the clock generation system, and generating an acceleration status signal based on the monitored acceleration;
• in response to one or more of the PLL status signal and the acceleration status signal indicating a shock event, generating the system clock based on the oscillator clock;
• and
• after a delay, generating the system clock based on the PLL clock, wherein the delay starts with generating the system clock based on the oscillator clock.