Partial array sparing in a memory

A design structure tangibly embodied in a non-transitory machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• an integrated circuit, including:
• a semiconductor substrate;
• integrated circuitry on the semiconductor substrate, wherein the integrated circuitry includes a memory array including:
• a plurality of memory macros including at least first and second memory macros, wherein each of the plurality of memory macros includes:
• multiple partial arrays, wherein each of the multiple partial arrays is associated with its own respective write driver, sense amplifier, and output buffer;
• and
• a shared macro controller configured to control read and write access to the multiple partial arrays;
• and
• spare access control logic configured to direct an access to a first partial array in the first memory macro to a second partial array in the second memory macro.

A method of operating a memory array, comprising:

• in a memory array including a plurality of memory macros including at least first and second memory macros, wherein each of the plurality of memory macros includes:
• multiple partial arrays, wherein each of the multiple partial arrays is associated with its own respective write driver, sense amplifier, and output buffer;
• and
• a shared macro controller configured to control read and write access to the multiple partial arrays,
• replacing the first partial array in the first memory macro with a second partial array in the second memory macro in a partial sparing event;
• and
• thereafter, a spare access control circuit in the memory array directing an access to the first partial array in the first memory macro to the second partial array in the second memory macro.