A storage controller system that controls solid state storage, comprising:
- a hard error correction decoder;
- a soft error correction decoder;
- and
- a processor that:
- determines a next read threshold based at least in part on a level count disparity, wherein the level count disparity is determined based at least in part on an expected count and an observed count;
- determines whether to switch from performing error correction decoding using the hard error correction decoder to the soft error correction decoder;
- and
- in the event it is determined to switch from performing error correction decoding using the hard error correction decoder to the soft error correction decoder:
- receives a plurality of read data at increments of Δ, wherein:
- a plurality of reads is performed on the solid state storage at integer increments of Δ to obtain the plurality of read data at increments of Δ;
- and
- Δ is a smallest voltage increment supported by the solid state storage;
- determines a plurality of adjacent difference counts based at least in part on the plurality of read data at increments of Δ;
- and
- determines a second next read threshold based at least in part on an inversely weighted average and the plurality of adjacent difference counts, wherein:
- a read is performed on the solid state storage using the second next read threshold to obtain second read data;
- and
- the soft error correction decoder performs error correction decoding on the second read data.