Using built-in self test or test results to identify weak memory bits and enable assist circuits when necessary
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorCormac Michael O'Connell
Life of this patent
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Abstract
A semiconductor device and a method of operating the semiconductor device and circuit are disclosed. In one aspect, the semiconductor device includes a memory array comprising a first memory cell and a second memory cell. The second memory cell has an operational characteristic different than that of the first memory cell. The semiconductor device includes a first write circuit configured to write first data to the first memory cell. The semiconductor device includes a second write circuit configured to write second data to the second memory cell, wherein the second write circuit is selectively configured to compensate for the operational characteristic of the second memory cell.
Claims20
A semiconductor device, comprising:
- a memory array comprising a first memory cell and a second memory cell, the second memory cell having an operational characteristic different than that of the first memory cell;
- a first write driver circuit configured to write first data to the first memory cell, the first write driver circuit coupled with a first write assist enable circuit;
- a second write driver circuit configured to write second data to the second memory cell, wherein the second write driver circuit is coupled to a second write assist enable circuit;
- and
- a write assist configuration circuit configured to shift configuration data through a shift register of the first write assist enable circuit and the second write assist enable circuit to designate the second write driver circuit for activation, causing the second write assist enable circuit to configure the second write driver circuit to compensate for the operational characteristic of the second memory cell.
A memory circuit, comprising:
- a write driver device configured to write input data to one of a first column or a second column of a memory array;
- a write assist circuit configured to cause the write driver device to selectively operate at one of a first voltage or a second voltage;
- a write assist enable circuit comprising a shift register and configured to activate the write assist circuit based on an indication that the first column or the second column comprises a memory cell having a defect;
- and
- a write assist configuration circuit configured to shift configuration data through the shift register of the write assist enable circuit, causing the write assist enable circuit to designate the first column or the second column as having the defect.
A method, comprising:
- shifting, by a write assist configuration circuit, configuration data through a shift register of a first write assist enable circuit and a second write assist enable circuit, the configuration data comprising an indication that a memory cell of a memory array has a predetermined operational characteristic;
- detecting, by the first write assist enable circuit, a write operation for a row or column of the memory array including the memory cell having the predetermined operational characteristic;
- and
- selectively activating, by the first write assist enable circuit, a write assist circuit to compensate for the predetermined operational characteristic of the memory cell during the write operation based on the indication.
Dependencies are inferred from the claim text.