Non-volatile read refresh operation comprising discharging a plurality of word lines
AssigneeSK hynix Inc.
InventorsSung Hyun Hwang, Jae Hyeon Shin
Life of this patent
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Abstract
A memory system includes: a nonvolatile memory device including a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines; and a controller configured to control the nonvolatile memory device to perform a read operation on the plurality of memory blocks, wherein the read operation includes: a first operation of supplying a first voltage level to the plurality of word lines, a second operation of discharging the plurality of word lines to a second voltage level, a third operation of supplying a third voltage level less than the first voltage level to the plurality of word lines, and a fourth operation of discharging the plurality of word lines to a fourth voltage level.
Claims13
A memory system comprising:
- a nonvolatile memory device including a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines;
- and
- a controller configured to control the nonvolatile memory device to perform a read refresh operation on the plurality of memory blocks,
- wherein the read refresh operation includes:
- a first operation of driving a first voltage level to each of the plurality of word lines,
- a second operation of discharging each of the plurality of word lines to a second voltage level,
- a third operation of driving a third voltage level less than the first voltage level to each of the plurality of word lines, and
- a fourth operation of discharging each of the plurality of word lines to a fourth voltage level,
- wherein the first voltage level is a level higher by a set level than a voltage level for turning on a memory cell with a highest threshold voltage level among the plurality of memory cells, and
- wherein the third voltage level is a level for turning on some of the plurality of memory cells and turning off the others.
A nonvolatile memory device comprising:
- a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines;
- and
- a control circuit configured to perform a read refresh operation on a selected memory block among the plurality of memory blocks,
- wherein the read refresh operation includes:
- a first operation of driving a first voltage level to each of the plurality of word lines,
- a second operation of discharging each of the plurality of word lines to a second voltage level,
- a third operation of driving a third voltage level less than the first voltage level to each of the plurality of word lines, and
- a fourth operation of discharging each of the plurality of word lines to a fourth voltage level,
- wherein the first voltage level is a level higher by a set level than a voltage level for turning on a memory cell with a highest threshold voltage level among the plurality of memory cells, and
- wherein the third voltage level is a level for turning on some of the plurality of memory cells and turning off the others.
An operating method of a nonvolatile memory device including a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines, the operating method comprising:
- selecting at least one of the plurality of memory blocks as a selected memory block;
- and
- performing a read refresh operation on the selected memory block,
- wherein the read refresh operation includes:
- a first operation of driving a first voltage level to each of the plurality of word lines,
- a second operation of discharging, after the first operation, each of the plurality of word lines to a second voltage level,
- a third operation of driving, after the second operation, a third voltage level less than the first voltage level to each of the plurality of word lines, and
- a fourth operation of discharging, after the third operation, each of the plurality of word lines to a fourth voltage level,
- wherein the first voltage level is a level higher by a set level than a voltage level for turning on a memory cell with a highest threshold voltage level among the plurality of memory cells, and
- wherein the third voltage level is a level for turning on some of the plurality of memory cells and turning off the others.
Dependencies are inferred from the claim text.