US 12,744,089 B2Granted

Semiconductor memory device

AssigneeKioxia Corporation

InventorsYuki Sakaguchi, Tatsuo Izumi, Masashi Yoshida

Life of this patent

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Abstract

A semiconductor memory device includes a first wiring, a first memory transistor connected to the first wiring, a first transistor connected between the first wiring and the first memory transistor, a second transistor connected between the first wiring and the first transistor, and second to fourth wirings respectively connected to gate electrodes of the first memory transistor, the first transistor, and the second transistor. From a first timing to a second timing, a voltage difference between the first wiring and the third wiring is maintained at a predetermined value, a voltage difference between the third wiring and the fourth wiring is maintained at a predetermined value, a voltage of the first wiring becomes larger than a voltage of the third wiring, and the voltage of the third wiring becomes larger than a voltage of the fourth wiring.

Claims24

Dependent claims

A semiconductor memory device, comprising:

a first wiring;
a first memory transistor connected to the first wiring;
a first transistor connected between the first wiring and the first memory transistor;
a second transistor connected between the first transistor and the first memory transistor;
a second wiring connected to a gate electrode of the first memory transistor;
a third wiring connected to a gate electrode of the first transistor;
a fourth wiring connected to a gate electrode of the second transistor;
a second memory transistor connected to the first wiring and having a gate electrode connected to the second wiring;
a third transistor connected between the first wiring and the second memory transistor;
a fourth transistor connected between the third transistor and the second memory transistor;
a fifth wiring connected to a gate electrode of the third transistor;
a sixth wiring connected to a gate electrode of the fourth transistor;
an insulating layer disposed between the gate electrode of the first transistor and the gate electrode of the third transistor;
a source line connected to the first memory transistor and the second memory transistor;
a fifth transistor connected between the source line and the first memory transistor;
a sixth transistor connected between the source line and the second memory transistor;
a seventh wiring connected to a gate electrode of the fifth transistor;
an eighth wiring connected to a gate electrode of the sixth transistor;
and
a control circuit configured to execute an erase operation that erases data of the first memory transistor, wherein
the third wiring is electrically connected to the fifth wiring,
the fourth wiring is electrically insulated from the sixth wiring,
the seventh wiring is electrically connected to the eighth wiring,
a transistor is not provided between the first transistor and the first wiring,
a transistor is not provided between the third transistor and the first wiring, and
in the erase operation, in the control circuit:
voltages of the fourth wiring and the sixth wiring transit from a first voltage to a second voltage larger than the first voltage;
voltages of the third wiring and the fifth wiring transit from a third voltage to a fourth voltage larger than the third voltage;
and
the second voltage is larger than the fourth voltage.

27 more elements

A method for controlling a semiconductor memory device, the semiconductor memory device comprising:

a first wiring;
a first memory transistor connected to the first wiring;
a first transistor connected between the first wiring and the first memory transistor;
a second transistor connected between the first transistor and the first memory transistor;
a second wiring connected to a gate electrode of the first memory transistor;
a third wiring connected to a gate electrode of the first transistor;
a fourth wiring connected to a gate electrode of the second transistor;
a second memory transistor connected to the first wiring and having a gate electrode connected to the second wiring;
a third transistor connected between the first wiring and the second memory transistor;
a fourth transistor connected between the third transistor and the second memory transistor;
a fifth wiring connected to a gate electrode of the third transistor;
a sixth wiring connected to a gate electrode of the fourth transistor;
an insulating layer disposed between the gate electrode of the first transistor and the gate electrode of the third transistor;
a source line connected to the first memory transistor and the second memory transistor;
a fifth transistor connected between the source line and the first memory transistor;
a sixth transistor connected between the source line and the second memory transistor;
a seventh wiring connected to a gate electrode of the fifth transistor;
an eighth wiring connected to a gate electrode of the sixth transistor;
and
a control circuit configured to execute an erase operation that erases data of the first memory transistor, wherein
the third wiring is electrically connected to the fifth wiring,
the fourth wiring is electrically insulated from the sixth wiring,
the seventh wiring is electrically connected to the eighth wiring,
a transistor is not provided between the first transistor and the first wiring,
a transistor is not provided between the third transistor and the first wiring, and
in the erase operation, in the control circuit:
voltages of the fourth wiring and the sixth wiring transit from a first voltage to a second voltage larger than the first voltage;
voltages of the third wiring and the fifth wiring transit from a third voltage to a fourth voltage larger than the third voltage;
and
the second voltage is larger than the fourth voltage.

27 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/920,516Filed 18 Oct 2024 · continuation
Priority: JP 2019-0411747 Mar 2019
Published: US 2025/0046379 A16 Feb 2025
Granted: 22 Sep 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 16/14
Programming or data input circuits: circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/16
Circuits for erasing electrically, e.g. erase voltage switching circuits: for erasing blocks, e.g. arrays, words, groups
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/32
Auxiliary circuits, e.g. for writing into memory: timing circuits

Family

Application16/569,379Parent of this continuation · filed 12 Sep 2019
Application17/223,202Parent of this division · filed 6 Apr 2021
US 10,991,431 B2Parent of this continuation · filed 27 Apr 2021
Application18/451,162Parent of this continuation · filed 17 Aug 2023
US 11,769,553 B2Parent of this division · filed 26 Sep 2023
US 2025/0046379 A1Pre-grant publication · published 6 Feb 2025
US 12,148,479 B2Parent of this continuation
Application18/451,162Parent of this division
Application17/223,202Parent of this continuation
US 2020/0286564 A1Published application
US 2021/0225449 A1Published application
US 2023/0395154 A1Published application
US 12,744,089 B2This patent

From the US filing history. Foreign family members aren’t listed.