Memory device and operation method applied for data search

An operation method applied to a memory device comprising a memory array and a control circuit, wherein the memory array comprises M*N memory cells, wherein the memory array is electrically connected to the control circuit through M first bit-lines, M second bit-lines, M first source lines, M second source lines, and N word lines, and a memory cell among the M*N memory cells comprises a first transistor and a second transistor, wherein the operation method comprises steps of:

• the control circuit programming M memory cells among the M*N memory cells, located at the n-th row, to store an in-memory data, wherein the in-memory data comprises M in-memory bits, and a threshold voltage of the first transistor and a threshold voltage of the second transistor are programmed according to an m-th in-memory bit among the M in-memory bits;
• receiving, by the control circuit, a search input comprising M search bits from a host device;
• the control circuit setting a first search voltage and a second search voltage according to an m-th search bit among the M search bits;
• applying a select voltage to an n-th word line among the N word lines, wherein control terminals of the first transistor and a second transistor are electrically connected to the n-th word line;
• applying a pass-through voltage to other (N−1) word lines among the N word lines;
• applying the first search voltage to an m-th first bit-line, wherein an m-th first sensing current is selectively generated in response to the first search voltage and the threshold voltage of the first transistor;
• applying the second search voltage to an m-th second bit-line, wherein an m-th second sensing current is selectively generated in response to the second search voltage and the threshold voltage of the second transistor;
• receiving the m-th first sensing current through an m-th first source line;
• receiving the m-th second sensing current through an m-th second source line;
• generating a sensing circuit output based on the m-th first sensing current and the m-th second sensing current;
• and
• the control circuit receiving the sensing circuit output,
• wherein the M memory cells are divided into P memory partitions, the P in-memory data partitions are identical, and each of the P memory partitions corresponds to Q bit-positions,
• wherein the in-memory data comprises P in-memory data partitions, and each of the P in-memory data partitions is stored at one of the P memory partitions,
• wherein P, Q, M, N, m, and n are positive integers, m is smaller than or equivalent to M, n is smaller than or equivalent to N, and M is equivalent to a product of P and Q.

A memory device, comprising:

• a memory array, comprising:
• M*N memory cells, wherein a memory cell among the M*N memory cells is located at an m-th column and n-th row, and the memory cell comprises a first transistor and a second transistor;
• M first bit-lines, wherein an m-th first bit-line among the M first bit-lines is electrically connected to a first terminal of the first transistor, and a first search voltage is applied to the m-th first bit-line;
• M second bit-lines, wherein an m-th second bit-line among the M second bit-lines is electrically connected to a first terminal of the second transistor, and a second search voltage is applied to the m-th second bit-line;
• M first source lines, wherein an m-th first source line among the M first source lines is electrically connected to a second terminal of the first transistor, and an m-th first sensing current is selectively generated in response to the first search voltage and a threshold voltage of the first transistor;
• M second source lines, wherein an m-th second source line among the M second source lines is electrically connected to a second terminal of the second transistor, and an m-th second sensing current is selectively generated in response to the second search voltage and a threshold voltage of the second transistor, wherein
• M memory cells among the M*N memory cells located at the n-th row are programmed to store an in-memory data, and the in-memory data comprises M in-memory bits, wherein
• the threshold voltage of the first transistor and the threshold voltage of the second transistor are programmed according to an m-th in-memory bit among the M in-memory bits;
• and
• N word lines, wherein control terminals of the first transistor and the second transistor are electrically connected to an n-th word line among the N word lines, a select voltage is applied to the n-th word line, and a pass-through voltage is applied to other (N−1) word lines among the N word lines;
• and
• a control circuit, electrically connected to the memory array through the M first bit-lines, the M second bit-lines, the M first source lines, the M second source lines, and the N word lines, wherein the control circuit comprises:
• a sensing circuit, configured to receive the m-th first sensing current through the m-th first source line, receive the m-th second sensing current through the m-th second source line, and generate a sensing circuit output representing whether the m-th first sensing current and the m-th second sensing current are generated, wherein the sensing circuit comprises:
• M first sensing-units, respectively electrically connected to the M first source lines, wherein an m-th first sensing-unit among the M first sensing-units converts the m-th first sensing current to an m-th first sensing-unit output;
• M second sensing-units, respectively electrically connected to the M second source lines, wherein an m-th second sensing-unit among the M second sensing-units converts the m-th second sensing current to an m-th second sensing-unit output, wherein the m-th first sensing-unit output and the m-th second sensing-unit output are logic signals;
• and
• a total current counter, electrically connected to the M first sensing-units and the M second sensing-units, configured to generate the sensing circuit output based on the m-th first sensing-unit output and the m-th second sensing-unit output, wherein the sensing circuit output represents a number between 0 and M;
• and
• a memory controller, electrically connected to the memory array, the sensing circuit, and a host device, configured to receive a search input comprising M search bits from the host device, set the first search voltage and the second search voltage according to an m-th search bit among the M search bits, and receive the sensing circuit output,
• wherein M, N, m, and n are positive integers, m is smaller than or equivalent to M, and n is smaller than or equivalent to N.