3D cell and array structures

A memory cell array structure, comprising:

• a plurality of memory cells organized into a plurality of rows and columns, wherein each memory cell is configured to generate a cell current based on a received input signal and stored data;
• a plurality of input lines, wherein each input line is connected to memory cells in a selected row, and wherein the plurality of input lines form a plurality of input line groups;
• a plurality of output lines, wherein each output line is connected to memory cells in a selected column, and wherein the plurality of output lines form a plurality of output line groups;
• a selector configured to sequentially select the input line groups to limit a number of selected memory cells per output line in an output line group;
• a multiplexer having multiplexer inputs and multiplexer outputs, wherein the multiplexer inputs are connected to the output line groups, wherein the multiplexer is configured to sequentially select which of the output line groups are connected to the multiplexer outputs;
• neuron circuits connected to the multiplexer outputs, wherein the neuron circuits are configured to convert a summation of cell currents in a selected output line group into digital data;
• and
• wherein the memory cell array simulates a neural network in which the plurality of input lines simulate input layer neurons of the neural network, and the plurality of output lines simulate output layer neurons of the neural network.