Method for reading a multi-level non-volatile memory device, in particular a phase-change memory device, and multi-level non-volatile memory device
AssigneeSTMicroelectronics International N.V.
InventorsXavier Lecoq, Alin Razafindraibe
Life of this patent
Estimating the term…
Abstract
A multi-level non-volatile memory cell has N levels, N being even and greater than two, corresponding respectively to N logical data that can be stored in the memory cell and to N corresponding read current ranges. A datum stored in the memory cell is read by performing successive comparisons of a read current output by the memory cell with reference currents selected from a set of N−1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having the median value.
Claims6
A method for managing operation of a multi-level non-volatile memory cell, the multi-level non-volatile memory cell comprising a phase-change type memory cell having N levels, N being even and greater than two, corresponding respectively to N logical data values that can be stored in the multi-level non-volatile memory cell and to N corresponding read current ranges, the method comprising:
- reading the multi-level non-volatile memory cell by performing successive comparisons of a read current output by the multi-level non-volatile memory cell on a read bit line with reference currents selected from a set of N−1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with a reference current having a median value;
- and
- generating the reference currents by:
- providing a reference memory cell connected to a reference bit line, the reference memory cell comprising a phase-change type memory cell that is structurally identical to the multi-level non-volatile memory cell;
- placing the reference memory cell in a SET state;
- and
- applying a plurality of different reference voltages to the reference bit line to cause the reference memory cell to correspondingly generate the reference currents.
A multi-level non-volatile memory device, comprising:
- at least one non-volatile memory cell comprising a phase-change type memory cell having N levels, N being even and greater than two, corresponding respectively to N logical data values that can be stored in the multi-level non-volatile memory cell and to N corresponding read current ranges;
- and
- a reading circuit configured to read the multi-level non-volatile memory cell by carrying out successive comparisons of a read current output by the multi-level non-volatile memory cell on a read bit line with reference currents selected from a set of N−1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having a median current value;
- wherein the reading circuit comprises:
- a reference memory cell connected to a reference bit line, the reference memory cell comprising a phase-change type memory cell that is structurally identical to the multi-level non-volatile memory cell;
- wherein the reference memory cell is programmed in a SET state;
- and
- a voltage generator circuit configured to apply a plurality of different reference voltages to the reference bit line to cause the reference memory cell to correspondingly generate the reference currents.
Dependencies are inferred from the claim text.