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US 12,744,076 B2Granted
Main word line driver and memory apparatus using the same
AssigneeSK hynix Inc.
InventorHo Seok Em
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Abstract
A memory apparatus includes a first main word line signal, a second main word line signal, and a word line driver. The first main word line signal is coupled to a first sub-word line driver block including n sub-word line drivers. The second main word line signal is coupled to a second sub-word line driver block including n sub-word line drivers. The main word line driver is configured to selectively enable one of the first and second main word line signals.
Claims16
A main word line driver comprising:
- an enable control signal generation circuit configured to generate an enable control signal based on a pre-decoding signal;
- a first driver configured to enable a first main word line signal based on the enable control signal and an even selection signal;
- and
- a second driver configured to enable a second main word line signal based on the enable control signal and an odd selection signal,
- wherein the first transistor receives the enable control signal to apply a first power supply voltage to a first output node, and the first main word line signal is output from the first output node,
- the second transistor receives the enable control signal,
- the third transistor receives the even selection signal,
- the second transistor and the third transistor are coupled in series between the first output node and a ground voltage, and
- the fourth transistor receives the first main word line signal to couple the enable control signal and the ground voltage.
6 more elements
A memory apparatus comprising:
- a plurality of sequentially stacked memory cell arrays each comprising a plurality of word lines;
- a sub-word line driver block configured to enable at least one word line among the plurality of word lines of each of the plurality of memory cell arrays based on a first main word line signal, a second main word line signal, and a sub-word line selection signal;
- and
- a main word line driver block configured to enable the first and second main word line signals based on a pre-decoding signal and an even and odd selection signal,
- wherein the sub-word line driver block comprises a first sub-word line driver block configured to enable first word lines of the plurality of memory cell arrays and a second sub-word line driver block configured to enable second word lines of the plurality of memory cell arrays, and
- wherein each of the first and second sub-word line driver blocks comprises a number of sub-word line drivers equal to a number of pluralities of memory cell arrays that have been stacked.
3 more elements
A main word line driver comprising:
- an enable control signal generation circuit configured to drive a first node to a ground voltage when a pre-decoding signal is asserted and to drive an enable control signal to a voltage level of a first power supply voltage based on a voltage level of the first node;
- a first driver configured to enable a first main word line signal based on the enable control signal and an even selection signal;
- and
- a second driver configured to enable a second main word line signal based on the enable control signal and an odd selection signal,
- wherein the enable control signal generation circuit is configured to drive the enable control signal to the ground voltage based on a word line off signal, and to provide a second power supply voltage to the first node based on the word line off signal.
2 more elements
Dependencies are inferred from the claim text.