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US 12,744,073 B2Granted
Semiconductor memory device performing refresh operation using multiple delay circuits
AssigneeMicron Technology, Inc.
InventorAtsushi Hatakeyama
Life of this patent
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Abstract
An example apparatus includes a plurality of pairs of input and output signal lines, a plurality of first delay circuits operatively connected between the plurality of input signal lines and the plurality of output signal lines, and a first selector circuit configured to connect a selected one of the plurality of first delay circuits between a selected one of the plurality of pairs of the input and output signal lines.
Claims16
An apparatus comprising:
- a plurality of input signal lines respectively paired with a plurality of output signal lines;
- a plurality of first delay circuits operatively connected between the plurality of input signal lines and the plurality of output signal lines;
- and
- a first selector circuit configured to connect a selected one of the plurality of first delay circuits between a selected one of the plurality of input signal lines and a respective one of the plurality of output signal lines,
- wherein a number of the plurality of first delay circuits is less than a number of the plurality of input signal lines,
- wherein the first selector circuit is configured to select one of the plurality of first delay circuits responsive to a first selection signal and select one of the plurality of input signal lines and the respective one of the plurality of output signal lines responsive to a second selection signal,
- wherein the first selection signal is updated each time a predetermined command is issued from outside, and
- wherein the predetermined command includes a refresh command and a refresh management command.
5 more elements
An apparatus comprising:
- a plurality of selector circuits;
- a plurality of delay circuits corresponding to the plurality of selector circuits, respectively;
- and
- a plurality of first OR gate circuits,
- wherein each of the plurality of selector circuits includes:
- a plurality of input gate circuits exclusively selected and each supplied with an associated one of a plurality of first control signals;
- a second OR gate circuit supplied with output signals of the plurality of input gate circuits to generate a second control signal;
- and
- a plurality of output gate circuits exclusively selected and supplied in common with a third control signal,
- wherein each of the plurality of delay circuits is configured to generate the third control signal responsive to the second control signal, and
- wherein each of the plurality of first OR gate circuits is supplied with output signals of the output gate circuits included in different ones of the plurality of selector circuits.
8 more elements
An apparatus comprising:
- a plurality of memory banks;
- and
- a center circuit including a plurality of timing adjusters, wherein the center circuit is configured to control a selected one of the plurality of memory banks so as to start performing a refresh operation responsive to an external command,
- wherein each of the plurality of memory banks is configured to activate a first control signal at a predetermined timing during the refresh operation,
- wherein the center circuit is configured to generate a second control signal by sending the first control signal to one of the plurality of timing adjusters,
- wherein each of the plurality of memory banks is configured to start performing a precharge operation responsive to the second control signal,
- wherein a connection relation between the plurality of memory banks and the plurality of timing adjusters is dynamically changed responsive to a third control signal, and
- wherein the third control signal is updated responsive to the external command.
5 more elements
Dependencies are inferred from the claim text.