US 12,744,071 B2 · Memory device including in-memory operation circuit and operating method thereof

Abstract

A memory device includes an in-memory operation circuit connected to a write word line, a plurality of write bit lines, a read word line, and a read bit line, and including bit cells. Each of the plurality of bit cells includes a first transistor having one end connected to a corresponding write bit line, the other end connected to a storage node, and a gate terminal connected to the write word line, and at least one second transistor having one end connected to the read bit line, the other end connected to the read word line, and a gate terminal connected to the storage node. A current value of turn-on current of the at least one second transistor included in each of the bit cells corresponds to a value obtained by multiplying a reference current value by a power of 2 that is different for each of the bit cells.

Claims20

Dependent claims

A memory device comprising:

an in-memory operation circuit connected to a write word line, a plurality of write bit lines, a read word line, and a read bit line, and including a plurality of bit cells;
wherein each of the plurality of bit cells comprises:
a first transistor having a first end connected to a corresponding write bit line among the plurality of write bit lines, a second end connected to a storage node, and a gate terminal connected to the write word line;
and at least one second transistor having a first end connected to the read bit line, a second end connected to the read word line, and a gate terminal connected to the storage node, wherein a current value of a turn-on current of the at least one second transistor included in each of the plurality of bit cells corresponds to a value obtained by multiplying a reference current value by a power of 2, and wherein the power of 2 is different for each of the plurality of bit cells.

1 more element

A method of operating a memory device including a plurality of bit cells, each of which includes a first transistor and at least one second transistor, the first transistor having a first end connected to a corresponding write bit line among a plurality of write bit lines, a second end connected to a storage node, and a gate terminal connected to a write word line;

and the at least one second transistor having a first end connected to a read bit line, a second end connected to a read word line, and a gate terminal connected to the storage node and providing a different turn-on current of each of the plurality of bit cells, the method comprising:
performing a multiplication operation of first operation target data stored in the storage nodes of the plurality of bit cells, and second operation target data, wherein the performing of the multiplication operation includes:
applying an off-voltage to the write word line in a first time period;
applying a ground voltage to the read word line in a second time period;
and applying a voltage having a magnitude associated with the second operation target data to the read bit line in a third time period.

2 more elements

Dependencies are inferred from the claim text.

Memory device including in-memory operation circuit and operating method thereof

Life of this patent

Memory device including in-memory operation circuit and operating method thereof

Life of this patent

Abstract

Claims20