Plate line drivers with a shared bias device
AssigneeMicron Technology, Inc.
InventorMakoto Kitagawa
Life of this patent
Estimating the term…
Abstract
A variety of applications can include apparatus having a memory device comprising plate select lines coupled to capacitors of memory cells of the memory device, plate line drivers coupled to the plate select lines, and a bias device coupled to each plate line driver. Use of a single bias device can allow for generation of robust current across multiple plate line drivers. The plate line drivers can be arranged with different formats that can operate with a single bias device. Plate select lines and the plate line driver can be structured in a scheme to balance the number of plate select lines and device counts for the plate line drivers.
Claims20
A memory device comprising:
- plate select lines coupled to capacitors of memory cells of the memory device;
- plate line drivers coupled to the plate select lines, each plate line driver including at least two transistors arranged in a series arrangement in the plate line driver;
- and
- a bias transistor coupled to each plate line driver of the plate line drivers such that the bias transistor is shared by the plate line drivers.
A memory device comprising:
- a memory array partitioned into subarrays of memory cells, each memory cell including a capacitor as a storage unit, each capacitor having a plate coupled to a plate line;
- plate select lines arranged in groups of plate select lines;
- plate line drivers coupled to the subarrays, each plate line driver assigned to a subarray, a given plate line driver including:
- a first transistor having a gate coupled to a first plate select line assigned to the given plate line driver;
- a second transistor coupled to the first transistor, the second transistor having a gate coupled to a second plate select line assigned to the given plate line driver, the first plate select line and the second plate select line being in a first group of the groups of plate select lines;
- a third transistor having a gate coupled to a third plate select line assigned to the given plate line driver;
- and
- a fourth transistor having a gate coupled to a fourth plate select line assigned to the given plate line driver, the third plate select line and the fourth plate select line being in a second group of the groups of plate select lines, the fourth transistor coupled in parallel to the third transistor, with a common node to the third transistor, the fourth transistor, and the second transistor coupled to a plate line to the subarray to which the given plate line driver is assigned;
- a bias transistor coupled to each plate line driver;
- and
- a controller to generate signals to the plate select lines to place a selected plate line in a selected status and place unselected plate lines in an unselected status.
A method comprising:
- generating signals to plate select lines of a memory device to select a specified plate line of the memory device based on an arrangement of the plate select lines with plate line drivers of the memory device, the memory device having a memory array arranged as subarrays of memory cells, each memory cell of a subarray including a capacitor as a storage unit, each capacitor having a plate coupled to a plate line assigned to the subarray;
- and
- providing a bias signal to a bias transistor coupled to each plate line driver of the plate line drivers coupled to the plate select lines with the bias transistor being shared by the plate line drivers.
Dependencies are inferred from the claim text.