Shift register unit, driving method thereof, and device

A shift register unit, comprising:

• an input circuit configured to provide a signal of an input signal terminal to a first node in response to a signal of a first clock signal terminal;
• a node control circuit, connected with the first node, a second node and the first clock signal terminal respectively;
• wherein the node control circuit is configured to provide the signal of the first clock signal terminal to the second node in response to a signal of the first node;
• a first control output circuit configured to control a signal of a third node according to a signal of a first control signal terminal and a signal of the second node;
• a second control output circuit, connected with the third node, a second reference signal terminal and a signal output terminal;
• an output circuit configured to provide a signal to the signal output terminal according to the signal of the first node;
• wherein the output circuit comprises an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
• a first electrode of the eleventh transistor is coupled to the input circuit, and a second electrode of the eleventh transistor is coupled to a gate electrode of the thirteenth transistor;
• a first electrode of the twelfth transistor is coupled to the first electrode of the eleventh transistor;
• wherein the eleventh transistor and the twelfth transistor are configured to provide a signal the gate electrode of the thirteenth transistor;
• wherein a gate electrode of the twelfth transistor and a gate electrode of the eleventh transistor are coupled to different signal terminals.