Three-dimensional memory array and preparation method thereof

A three-dimensional memory array, comprising memory cells arranged in an array, wherein in each memory cell:

• one end of the memory cell is connected to a word line WL, and the other end thereof is connected to a bit line BL, and a corresponding gating transistor is provided at a bottom of each word line WL, and the bottom of the word line WL is connected to a drain of the gating transistor;
• a gate of the gating transistor is connected to a gate line GL, and a source of the gating transistor is connected to a source line SL;
• and
• the bit line BL, the word line WL, the source line SL, and the gate line GL control a state of the memory cell;
• and
• the word line WL, the bit line BL, and the gate line GL are arranged in directions perpendicular to each other, and the source line SL and the bit line BL are arranged in directions parallel to each other;
• and
• wherein the bottom of each word line WL of the three-dimensional memory array is electrically connected to the drain of the gating transistor through at least one layer of connection holes, so that the three-dimensional memory array is isolated from the gating transistor and connected in alignment, wherein the word line WL arranged in a Z-axis direction is connected to a column of memory cells, and in a XY-axis plane direction, the memory cells of each layer are accessed through the bit lines BL of the layer, and
• the gating transistor is gated by applying a voltage through the gate line GL and the source line SL, wherein the gate line GL connects the gates of a row of gating transistors along a Y-axis direction, and the source line SL connects the sources of the gating transistors along a X-axis direction.