Drive circuit and display device
AssigneeSharp Display Technology Corporation
InventorsYohei Takeuchi, Tatsuya Kawasaki, Kengo Hara, Masafumi Sugino, Hajime Imai
Life of this patent
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Abstract
A unit circuit of a gate drive circuit includes first to fourth transistors. The first transistor outputs a drive signal to a gate line. The second transistor is a transistor to which a set signal is inputted and which charges a node. The third transistor is a transistor to which a first reset signal is inputted and which discharges the node to a ground potential. The fourth transistor is a transistor to which a second reset signal supplied at a time point later than the first reset signal is inputted and which discharges the node to a gate-off voltage.
Claims4
A drive circuit comprising a plurality of unit circuits that each output a drive signal to one of scanning signal lines of a scanning signal line group, wherein
- the unit circuits each include:
- a node;
- a first transistor that outputs the drive signal to the scanning signal line, wherein the node is connected to a gate electrode of the first transistor, a clock signal is applied to a source electrode of the first transistor, and a drain electrode of the first transistor is connected to the scanning signal line;
- a second transistor at which a set signal is inputted to the unit circuit, wherein the set signal is inputted to a gate electrode of the second transistor, and a drain electrode of the second transistor is connected to the node;
- a third transistor at which a first reset signal is inputted to the unit circuit, wherein the first reset signal is inputted to a gate electrode of the third transistor, a drain electrode of the third transistor is connected to the node, and a voltage lower than a gate-on voltage and higher than a gate-off voltage is applied to a source electrode of the third transistor;
- and
- a fourth transistor at which a second reset signal having a high level is inputted at a time point later than the first reset signal, wherein the second reset signal is inputted to a gate electrode of the fourth transistor, a drain electrode of the fourth transistor is connected to the node, and the gate-off voltage is applied to a source electrode of the fourth transistor.
Dependencies are inferred from the claim text.