Liquid crystal display device and electronic device including the same

A semiconductor device comprising:

• a first transistor;
• and
• a second transistor,
• wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a scan line,
• wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the scan line,
• wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line,
• wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a power supply line,
• wherein in a plan view, an area where a first conductive layer serving as the one of the source electrode and the drain electrode of the first transistor and a second conductive layer serving as a gate electrode of the first transistor overlapping with each other is larger than an area where a third conductive layer serving as the other of the source electrode and the drain electrode of the first transistor and the second conductive layer overlapping with each other,
• wherein in the plan view, an area where the first conductive layer serving as the one of the source electrode and the drain electrode of the second transistor and a fourth conductive layer serving as a gate electrode of the second transistor overlapping with each other is smaller than an area where a fifth conductive layer serving as the other of the source electrode and the drain electrode and the fourth conductive layer overlapping with each other,
• wherein in the plan view, the first conductive layer comprises a first region overlapping with the second conductive layer and sandwiched between regions of the third conductive layer,
• wherein in the plan view, the third conductive layer comprises a second region overlapping with the second conductive layer and sandwiched between regions of the first conductive layer, and
• wherein a width of the first conductive layer in the first region is larger than a width of the third conductive layer in the second region.