US 12,743,572 B2Granted

System and method for automatic generation of standard cells using satisfiability modulo theory solver

AssigneeSilvaco, Inc.

InventorsOsvaldo Martinello, Guilherme Simoes Schlinker, Marcos Henrique Backes

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Abstract

An electronic design automation tool and method of operating the same are provided for placement and routing of intra-cell devices in integrated circuits (ICs). Generally the method includes: receiving inputs, creating an instance of a Satisfiability Modulo Theory (SMT) problem for placement and routing by translating the inputs into a set of SMT constraints relating to the placement of intra-cell transistors and routing for interconnects to intra-cell transistors, calling a SMT solver and using the set of SMT constraints generating a solution to the SMT problem, and if the solution satisfies requirements of the inputs and a predetermined area requirement specified by a user, creating and outputting a layout for placement and routing of intra-cell transistors in the IC. The process may be repeated until a predetermined number of ranked solutions or an optimal solution is found. Other embodiments are also disclosed.

Claims17

Dependent claims

A method for placement and routing of intra-cell transistors in an integrated circuit (IC), the method comprising:

receiving inputs including a netlist, template definitions and technology design rules;
creating a first instance of a Satisfiability Modulo Theory (SMT) problem for placement and routing by translating the inputs into a set of SMT constraints relating to the placement of a number of intra-cell transistors and routing for interconnects to the number of intra-cell transistors;
calling a SMT solver and using the set of SMT constraints generating a first solution to the SMT problem;
if the first solution satisfies requirements of the inputs and a predetermined area requirement specified by a user, creating and outputting a first layout for placement and routing of the number of intra-cell transistors in the IC;
determining whether a predetermined number of layouts has been created;
creating another instance of the SMT problem;
calling the SMT solver and generating another solution;
evaluating the solution against the requirements of the inputs and the predetermined area requirements;
creating and outputting another layout for placement and routing of the number of intra-cell transistors in the IC;
repeating the creating of instances of the SMT problem, generating of solutions, and creating and outputting of layouts until the predetermined number of layouts has been created;
ranking the layouts created based on predefined metrics including one or more of a number of masks needed for the layout, area required for the layout, and performance of the IC;
and
outputting the ranked layouts for the placement and routing of intra-cell transistors in the integrated circuit (IC).

10 more elements

A method for placement and routing of intra-cell transistors in an integrated circuit (IC), the method comprising:

receiving inputs including a netlist of components available for use in the IC, template definitions of the components and a predetermined area requirement for the IC specified by a user, and technology design rules specifying design requirements for the components;
creating a first instance of a Satisfiability Modulo Theory (SMT) placement problem by translating the inputs into a first set of SMT constraints relating to the placement of a number of intra-cell transistors in the IC;
calling a first SMT solver and generating a first solution to the SMT placement problem;
if the first solution to the SMT placement problem satisfies requirements of the inputs, creating a first instance of a SMT placement and routing problem using the first solution to the SMT placement problem;
calling a second SMT solver and generating a first solution to the SMT placement and routing problem;
and
if the first solution to the SMT placement and routing problem satisfies requirements of the inputs, creating and outputting a first layout for placement and routing of intra-cell transistors in the IC.

4 more elements

A non-transitory computer-readable media having program instructions for placement and routing of intra-cell transistors in an integrated circuit (IC), the computer readable media comprising:

program instructions for receiving inputs including a netlist, template definitions and technology design rules;
program instructions for creating a first instance of a Satisfiability Modulo Theory (SMT) problem for placement and routing by translating the inputs into a set of SMT constraints relating to the placement of a number of intra-cell transistors and routing for interconnects to the number of intra-cell transistors;
program instructions for calling a SMT solver and using the set of SMT constraints generating a first solution to the SMT problem;
if the first solution satisfies requirements of the inputs and a predetermined area requirement specified by a user, program instructions for creating and outputting a first layout for placement and routing of the number of intra-cell transistors in the IC;
program instructions for determining whether a predetermined number of layouts has been created;
program instructions for creating another instance of the SMT problem;
program instructions for calling the SMT solver and generating another solution;
program instructions for evaluating another solution against the requirements of the inputs and the predetermined area requirements;
program instructions for creating and outputting another layout for placement and routing of the number of intra-cell transistors in the IC;
program instructions for repeating the creating of instances of the SMT problem, generating of solutions, and creating and outputting of layouts until the predetermined number of layouts has been created;
program instructions for ranking the layouts created based on predefined metrics including one or more of a number of masks needed for the layout, area required for the layout, and performance of the IC;
and
program instructions for outputting the ranked layouts for the placement and routing of intra-cell transistors in an integrated circuit (IC).

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/268,017Filed 15 Dec 2021 · us provisional application
Priority: 16 Dec 2020
Published: US 2025/0077758 A16 Mar 2025
Granted: 22 Sep 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 30/39
Circuit design: circuit design at the physical level
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking
G06F 30/394
Circuit design at the physical level: routing