US 12,743,571 B2 · Method and system for simulating and verifying layout based on distribution

Abstract

A method for simulating a layout of an integrated circuit manufactured by a semiconductor process includes extracting a plurality of pattern layouts from layout data that defines the layout, generating training data by amplifying the plurality of pattern layouts and at least one parameter provided from the semiconductor process, generating sample data by sampling the training data, generating feature data including a three-dimensional array from the sample data, providing the sample data and the feature data to a simulator and a machine learning model, respectively, and training the machine learning model based on an output of the machine learning model and an output of the simulator.

Claims20

Dependent claims

A method for simulating a layout of an integrated circuit manufactured by a semiconductor process, the method comprising:

extracting a plurality of pattern layouts from layout data that defines the layout;
generating training data by amplifying the plurality of pattern layouts and at least one parameter provided from the semiconductor process;
generating sample data by sampling the training data;
generating feature data including a three-dimensional array from the sample data;
providing the sample data and the feature data to a simulator and a machine learning model, respectively;
and
training the machine learning model based on an output of the machine learning model and an output of the simulator.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/151,051Filed 6 Jan 2023

Priority

KR 10-2022-000869120 Jan 2022

Published

US 2023/0229841 A120 Jul 2023

Granted

22 Sep 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/27
Design optimisation, verification or simulation: using machine learning, e.g. artificial intelligence, neural networks, support vector machines…
G06F 30/367
Circuit design at the analogue level: design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE],…
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…

Method and system for simulating and verifying layout based on distribution

Life of this patent

Method and system for simulating and verifying layout based on distribution

Life of this patent

Abstract

Claims20