Generative self-supervised learning to transform circuit netlists
AssigneeNVIDIA Corporation
InventorsSiddhartha Nath, Haoxing Ren, Geraldo Pradipta, Corey Hu, Tian Yang
Life of this patent
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Abstract
Self-supervised machine learning is applied to combinational gate sizing based on an input circuit netlist. A transformer neural network architecture is disclosed to select gate sizes along paths of the network between primary inputs/outputs and/or sequential logic elements. The gate size selections may be optimized along dimensions such as path delay, path power consumption, and path circuit area.
Claims20
A transformer network for setting characteristics of gates in a circuit, the transformer network trained with gate characteristic distributions from a technology library, the transformer network comprising:
- an encoder configured to transform a sequence of gate types for a combinatorial circuit path in the circuit into encoder outputs;
- and
- a decoder configured to transform the encoder outputs, an effort level setting, and the sequence of gate types into a sequence of gate sizes for the combinatorial circuit path,
- wherein the effort level setting comprises a ratio of a median signal propagation delay and an actual signal propagation delay for the sequence of gate types.
A method for setting gate sizes in a circuit path, the method comprising:
- applying, to an encoder of a transformer network, gate types for each gate in the circuit path;
- applying, to a decoder of the transformer network, outputs of the encoder, and a token sequence comprising as a starting token an effort level and a first gate type of the gate type sequence, whereafter the token sequence comprises <predicted kth gate size, (k+1)th gate type> pairs and k is a gate position index in the circuit path;
- and
- the transformer network generating a sequence of the gate sizes from the gate types, effort level, and predicted gate sizes.
A system comprising:
- at least one processor;
- and
- at least one memory implementing logic to:
- operate a transformer network encoder to transform a sequence of gate types for a combinatorial circuit path into encoder outputs;
- apply the encoder outputs to a decoder of the transformer network;
- further apply to the decoder a token sequence comprising an effort level, the sequence of gate types, and predicted sizes for gates of the combinatorial circuit path;
- and
- operate the decoder to generate a sequence of gate sizes for the combinatorial circuit path from the gate types, effort level, encoder outputs, and predicted gate sizes.
A process comprising:
- operating a transformer network encoder to transform a sequence of gate types for a combinatorial circuit path into encoder outputs;
- applying the encoder outputs to a decoder of the transformer network;
- further applying to the decoder a token sequence comprising an effort level, the sequence of gate types, and predicted sizes for gates of the combinatorial circuit path;
- and
- operating the decoder to generate a sequence of gate sizes for the combinatorial circuit path from the gate types, effort level, encoder outputs, and predicted gate sizes.
Dependencies are inferred from the claim text.