Low-latency control interface and protocol
AssigneeQUALCOMM Incorporated
InventorsGordon Lee, Vijayakumar Ashok Dibbad, Louis Louie, Chris Rosolowski, Jennifer Hagstrom, Todd Robert Sutton, Orlando Santiago
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Abstract
Aspects of the disclosure relate to power management of a system-on-chip (SoC) and techniques of optimizing system performance and power management through power limits coordination via a low latency bus interface that provides a flexible protocol which enables high priority messages to facilitate power management. The protocol enables shallow power mitigation techniques to reduce the need of full mitigation of the apparatus.
Claims18
A system-on-chip (SoC), comprising:
- one or more processors;
- and
- a bus interface connecting between the one or more processors and a plurality of peripheral devices, the bus interface being configured to:
- receive an interrupt message from a peripheral device among the plurality of peripheral devices using an interrupt protocol,
- wherein a payload of the interrupt protocol comprises a plurality of timeslots that are respectively pre-assigned to a plurality of alert events associated with the plurality of peripheral devices, and
- wherein the interrupt message is inserted in a pre-assigned timeslot of the plurality of timeslots corresponding to an alert event among the plurality of alert events, wherein the alert event comprises at least one of a pre-current limit extension (PCLX) event, an imminent foldback flag (IFF) event, a battery current limiting (BCL) event.
A method of operating a bus interface at a system-on-chip (SoC), comprising:
- receiving an interrupt message from a peripheral device among a plurality of peripheral devices using an interrupt protocol,
- a payload of the interrupt protocol comprising a plurality of timeslots that are respectively pre-assigned to a plurality of alert events associated with the plurality of peripheral devices, and
- the interrupt message inserted in a pre-assigned timeslot of the plurality of timeslots corresponding to an alert event among the plurality of alert events, wherein the alert event comprises at least one of a pre-current limit extension (PCLX) event, an imminent foldback flag (IFF) event, a battery current limiting (BCL) event.
An apparatus comprising:
- a system-on-chip (SoC);
- and
- a power management integrated circuit (PMIC), the PMIC is configured to:
- control a regulator to supply power to the SoC;
- communicate with the SoC using an interrupt protocol, wherein a payload of the interrupt protocol comprises a plurality of timeslots respectively pre-assigned to a plurality of power management events;
- and
- send an interrupt message to the SoC, wherein the interrupt message is inserted in a pre-assigned timeslot of the payload corresponding to a power management event among the plurality of power management events, wherein the alert event comprises at least one of a pre-current limit extension (PCLX) event, an imminent foldback flag (IFF event, a battery current limiting (BCL) event.
Dependencies are inferred from the claim text.