Memory device including command-address management circuit, method of operating the same, and memory system

A method of operating a memory device including a first memory plane and a second memory plane operating independently of each other, the method comprising:

• receiving a first command-address instructing an input/output (I/O) operation for the first memory plane through a first bus;
• performing an operation corresponding to the first command-address;
• receiving a second command-address instructing an I/O operation for a second memory plane through the first bus;
• storing the second command-address in a command-address queue based on a state of a second bus;
• and
• performing an operation corresponding to the second command-address.

A memory system comprising:

• a memory controller configured to generate a first command-address and a second command-address;
• a memory device configured to perform an operation in response to the first command-address and the second command-address;
• a first bus configured to provide the first command-address and the second command-address to the memory device from the memory controller;
• and
• a second bus configured to transfer data between the memory controller and the memory device, wherein
• the memory device includes,
• a memory cell array including a first memory plane and a second memory plane;
• a control logic circuit connected to the first bus and configured to receive the first command-address and the second command-address;
• an input/output (I/O) circuit connected to the second bus and configured to transmit and receive data to and from the memory controller;
• and
• a command-address management circuit configured to receive the second command-address through the control logic circuit based on a state of the second bus, wherein
• the command-address management circuit includes,
• a command-address queue configured to store the second command-address, and
• a monitoring circuit configured to monitor the state of the second bus.