Interleaving cache line data transfers and handling misses of speculatively fetched data

An apparatus comprising:

• a first cache configured to output data from a cache array to a data bus;
• and
• a cache controller configured to receive one or more data requests and control the first cache to:
• transfer, from the first cache in response to the one or more data requests, a portion of data of a first cache line to a second cache;
• interrupt transferring the portion of data of the first cache line by transferring a first portion of data of a second cache line to the second cache;
• and
• transfer, from the first cache to the second cache, a remaining portion of data of the first cache line.

A system comprising:

• a memory;
• a processor core configured to issue an instruction targeting a location in the memory;
• and
• a cache hierarchy interposing the memory and the processor core, the cache hierarchy including:
• a first cache;
• and
• a second cache that is a higher-level cache than the first cache, the first cache and second cache being coupled by a data bus, wherein the first cache is configured to:
• receive, by the first cache, one or more data requests from a requesting device;
• transfer, by the first cache in response to the one or more data requests, a portion of data of a first cache line to a second cache;
• interrupt transferring the portion of data of the first cache line by transferring a first portion of data of a second cache line to the second cache;
• and
• transfer, by the first cache, a remaining portion of data of the first cache line to the second cache.