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US 12,743,371 B2Granted
Input circuit, memory interface circuit and memory system
AssigneeSamsung Electronics Co., Ltd.
InventorsDongkyu Jung, Anil Kavala, Youngmin Jo, Chiweon Yoon
Life of this patent
Estimating the term…
Abstract
An input circuit includes a first input buffer connected to a corresponding data pin, a second input buffer connected to a data strobe pin, and a repeater configured to delay an output signal of the first input buffer, and further includes a first loop configured to correct a voltage offset of each of the first input buffer and the second input buffer, and a second loop configured to correct a delay offset of the repeater.
Claims20
A memory system comprising:
- a buffer chip;
- a memory controller configured to transmit and receive a data strobe signal and a data signal to and from the buffer chip;
- and
- a plurality of non-volatile memory devices configured to transmit and receive the data strobe signal and the data signal to and from the buffer chip, each non-volatile memory device including a memory interface circuit comprising a plurality of data pins and a data strobe pin, each data pin connected to a corresponding data signal line, the data signal line configured to carry one of bit values for each bit position of the data signal, and the data strobe pin connected to a data strobe signal line configured to carry the data strobe signal, the memory interface circuit further including a plurality of input circuits, and
- each input circuit comprising
- a first input buffer connected to a corresponding data pin,
- a second input buffer connected to the data strobe pin,
- a repeater configured to delay an output signal of the first input buffer,
- a first loop configured to correct a voltage offset of each of the first input buffer and the second input buffer, and
- a second loop configured to correct a delay offset of the repeater.
7 more elements
A memory interface circuit comprising:
- a plurality of data pins and a data strobe pin, each data pin connected to a corresponding data signal line, the data signal line configured to carry one of bit values for each bit position of a data signal, and the data strobe pin connected to a data strobe signal line configured to carry a data strobe signal, the memory interface circuit further includes a plurality of input circuits, and
- each input circuit including
- a first input buffer connected to a corresponding data pin,
- a second input buffer connected to the data strobe pin,
- a repeater configured to delay an output signal of the first input buffer,
- a first loop configured to correct a voltage offset of each of the first input buffer and the second input buffer, and
- a second loop configured to correct a delay offset of the repeater.
4 more elements
An input circuit comprising:
- a first input buffer connected to a corresponding data pin,
- a second input buffer connected to a data strobe pin, and
- a repeater configured to delay an output signal of the first input buffer,
- a first loop configured to correct a voltage offset of each of the first input buffer and the second input buffer, and
- a second loop configured to correct a delay offset of the repeater.
2 more elements
Dependencies are inferred from the claim text.