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US 12,743,303 B2Granted
Pseudorandom thread generation
AssigneeHuawei Technologies Co., Ltd.
InventorsJingliang Wang, Noah Sherrill
Life of this patent
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Abstract
Implementations are directed to methods, systems, and computer-readable media for scheduling threads for instruction sequence generation. In one aspect, scheduling threads for instruction sequence generation can include obtaining a model of a central processing unit (CPU) that includes a plurality of threads, wherein the model includes a plurality of model threads that correspond to the plurality of threads of the CPU. A seed value can be input into a pseudorandom number generator and in response to the input seed value, a sequence of pseudorandom values can be obtained from the pseudorandom number generator. Using the sequence of pseudorandom values and a thread scheduling algorithm, a thread execution order of the plurality of model can be generated.
Claims21
A computer-implemented method of scheduling threads for instruction sequence generation comprising:
- obtaining a model of a central processing unit (CPU) that includes a plurality of threads, wherein the model includes a plurality of model threads that correspond to the plurality of threads of the CPU, and wherein the model of the CPU is coded in a hardware description language;
- inputting, into a pseudorandom number generator, a seed value;
- obtaining, from the pseudorandom number generator and in response to the seed value, a sequence of pseudorandom values;
- generating, using the sequence of pseudorandom values and a deterministic thread scheduling algorithm, a thread execution order of the plurality of model threads;
- detecting an error in CPU simulation testing of the plurality of model threads;
- in response to the detecting:
- inputting, into the pseudorandom number generator, the seed value;
- obtaining, from the pseudorandom number generator and in response to the seed value, a second sequence of pseudorandom values, the second sequence of pseudorandom values being the same as the sequence of pseudorandom values based on the seed value;
- generating, using the sequence of pseudorandom values and the deterministic thread scheduling algorithm, a second thread execution order of the plurality of model threads, the second thread execution order of the plurality of model threads being the same as the thread execution order of the plurality of model threads based on the second sequence of pseudorandom values being the same as the sequence of pseudorandom values,
- wherein the deterministic thread scheduling algorithm receives a list of model thread IDs and the sequence of pseudorandom values as inputs and outputs the thread execution order, and
- wherein CPU design is modified to resolve the error after the generating the second thread execution order;
- and
- verifying resolution of the error in the modified CPU design using the seed value to generate a third thread execution order of the plurality of model threads, the third thread execution order of the plurality of model threads being the same as the thread execution order of the plurality of model threads.
10 more elements
A non-transitory computer-readable medium having instructions stored thereon which, when executed by one or more processors, cause the one or more processors to perform operations comprising:
- obtaining a model of a central processing unit (CPU) that includes a plurality of threads, wherein the model includes a plurality of model threads that correspond to the plurality of threads of the CPU, and wherein the model of the CPU is coded in a hardware description language;
- inputting, into a pseudorandom number generator, a seed value;
- obtaining, from the pseudorandom number generator and in response to the seed value, a sequence of pseudorandom values;
- generating, using the sequence of pseudorandom values and a deterministic thread scheduling algorithm, a thread execution order of the plurality of model threads;
- detecting an error in CPU simulation testing of the plurality of model threads;
- in response to the detecting:
- inputting, into the pseudorandom number generator, the seed value;
- obtaining, from the pseudorandom number generator and in response to the seed value, a second sequence of pseudorandom values, the second sequence of pseudorandom values being the same as the sequence of pseudorandom values based on the seed value;
- generating, using the sequence of pseudorandom values and the deterministic thread scheduling algorithm, a second thread execution order of the plurality of model threads, the second thread execution order of the plurality of model threads being the same as the thread execution order of the plurality of model threads based on the second sequence of pseudorandom values being the same as the sequence of pseudorandom values,
- wherein the deterministic thread scheduling algorithm receives a list of model thread IDs and the sequence of pseudorandom values as inputs and outputs the thread execution order, and
- wherein CPU design is modified to resolve the error after the generating the second thread execution order;
- and
- verifying resolution of the error in the modified CPU design using the seed value to generate a third thread execution order of the plurality of model threads, the third thread execution order of the plurality of model threads being the same as the thread execution order of the plurality of model threads.
10 more elements
A system, comprising:
- one or more processors;
- and
- a non-transitory computer-readable medium device coupled to the one or more processors and having instructions stored thereon which, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
- obtaining a model of a central processing unit (CPU) that includes a plurality of threads, wherein the model includes a plurality of model threads that correspond to the plurality of threads of the CPU, and wherein the model of the CPU is coded in a hardware description language;
- inputting, into a pseudorandom number generator, a seed value;
- obtaining, from the pseudorandom number generator and in response to the seed value, a sequence of pseudorandom values;
- and
- generating, using the sequence of pseudorandom values and a deterministic thread scheduling algorithm, a thread execution order of the plurality of model threads;
- detecting an error in CPU simulation testing of the plurality of model threads;
- in response to the detecting:
- inputting, into the pseudorandom number generator, the seed value;
- obtaining, from the pseudorandom number generator and in response to the seed value, a second sequence of pseudorandom values, the second sequence of pseudorandom values being the same as the sequence of pseudorandom values based on the seed value;
- generating, using the sequence of pseudorandom values and the deterministic thread scheduling algorithm, a second thread execution order of the plurality of model threads, the second thread execution order of the plurality of model threads being the same as the thread execution order of the plurality of model threads based on the second sequence of pseudorandom values being the same as the sequence of pseudorandom values,
- wherein the deterministic thread scheduling algorithm receives a list of model thread IDs and the sequence of pseudorandom values as inputs and outputs the thread execution order, and
- wherein CPU design is modified to resolve the error after the generating the second thread execution order;
- and
- verifying resolution of the error in the modified CPU design using the seed value to generate a third thread execution order of the plurality of model threads, the third thread execution order of the plurality of model threads being the same as the thread execution order of the plurality of model threads.
14 more elements
Dependencies are inferred from the claim text.